16 Mbit (x8/x16) Concurrent SuperFlash GLS36VF1601E / GLS36VF1602E GLS36VF1601E / 1602E16Mb (x8/x16) Concurrent SuperFlash Data Sheet FEATURES: Organized as 1M x16 or 2M x8 Block-Erase Capability Dual Bank Architecture for Concurrent Uniform 32 KWord blocks Read/Write Operation Erase-Suspend / Erase-Resume Capabilities 16 Mbit Bottom Sector Protection Security ID Feature - GLS36VF1601E: 12 Mbit + 4 Mbit Greenliant: 128 bits 16 Mbit Top Sector Protection User: 128 bits - GLS36VF1602E: 4 Mbit + 12 Mbit Fast Read Access Time Single 2.7-3.6V for Read and Write Operations 70 ns Superior Reliability Latched Address and Data Endurance: 100,000 cycles (typical) Fast Erase and Program (typical): Greater than 100 years Data Retention Sector-Erase Time: 18 ms Low Power Consumption: Block-Erase Time: 18 ms Active Current: 6 mA typical Chip-Erase Time: 35 ms Standby Current: 4 A typical Program Time: 7 s Auto Low Power Mode: 4 A typical Automatic Write Timing Hardware Sector Protection/WP Input Pin Internal V Generation PP Protects the 4 outermost sectors (8 KWord) End-of-Write Detection in the larger bank by driving WP low and unprotects by driving WP high Toggle Bit Data Polling Hardware Reset Pin (RST ) Ready/Busy pin Resets the internal state machine to reading CMOS I/O Compatibility array data Conforms to Common Flash Memory Interface (CFI) Byte Pin JEDEC Standards Selects 8-bit or 16-bit mode Flash EEPROM Pinouts and command sets Sector-Erase Capability Packages Available Uniform 2 KWord sectors 48-ball TFBGA (6mm x 8mm) Chip-Erase Capability 48-lead TSOP (12mm x 20mm) PRODUCT DESCRIPTION The GLS36VF1601E and GLS36VF1602E are 1M x16 or vertent write, the devices have on-chip hardware and Soft- 2M x8 CMOS Concurrent Read/Write Flash Memory man- ware Data Protection schemes. Designed, manufactured, ufactured with Greenliants proprietary, high performance and tested for a wide spectrum of applications, these CMOS SuperFlash memory technology. The split-gate cell devices are offered with a guaranteed endurance of 10,000 design and thick oxide tunneling injector attain better reli- cycles. Data retention is rated at greater than 100 years. ability and manufacturability compared with alternate These devices are suited for applications that require con- approaches. The devices write (Program or Erase) with a venient and economical updating of program, configura- 2.7-3.6V power supply and conform to JEDEC standard tion, or data memory. For all system applications, the pinouts for x8/x16 memories. devices significantly improve performance and reliability, Featuring high performance Program, these devices pro- while lowering power consumption. Since for any given vide a typical Program time of 7 sec and use the Toggle voltage range, the SuperFlash technology uses less cur- Bit, Data Polling, or RY/BY to detect the completion of rent to program and has a shorter erase time, the total the Program or Erase operation. To protect against inad- energy consumed during any Erase or Program operation 2010 Greenliant Systems, Ltd. www.greenliant.com S71274-05-000 05/1016 Mbit Concurrent SuperFlash GLS36VF1601E / GLS36VF1602E Data Sheet is less than alternative flash technologies. These devices Concurrent Read/Write Operation also improve flexibility while lowering the cost for program, The dual bank architecture of these devices allows the data, and configuration storage applications. Concurrent Read/Write operation whereby the user can SuperFlash technology provides fixed Erase and Program read from one bank while programming or erasing in the times, independent of the number of Erase/Program other bank. For example, reading system code in one bank cycles that have occurred. Therefore the system software while updating data in the other bank. or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose TABLE 1: Concurrent Read/Write State Erase and Program times increase with accumulated Bank 1 Bank 2 Erase/Program cycles. Read No Operation To meet high-density, surface-mount requirements, these Read Write devices are offered in 48-ball TFBGA and 48-lead TSOP Write Read packages. See Figures 6 and 7 for pin assignments. Write No Operation No Operation Read Device Operation No Operation Write Memory operation functions are initiated using standard Note: For the purposes of this table, write means to perform Block- microprocessor write sequences. A command is written by or Sector-Erase or Program operations as applicable to the asserting WE low while keeping CE low. The address appropriate bank. bus is latched on the falling edge of WE or CE , which- ever occurs last. The data bus is latched on the rising edge Read Operation of WE or CE , whichever occurs first. The Read operation is controlled by CE and OE both have to be low for the system to obtain data from the out- Auto Low Power Mode puts. CE is used for device selection. When CE is high, These devices also have the Auto Lower Power mode the chip is deselected and only standby power is con- which puts them in a near standby mode within 500 ns after sumed. OE is the output control and is used to gate data data has been accessed with a valid Read operation. This from the output pins. The data bus is in a high impedance reduces the I active Read current to 4 A typically. While DD state when either CE or OE is high. Refer to the Read CE is low, the devices exit Auto Low Power mode with cycle timing diagram for further details (Figure 8). any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. 2010 Greenliant Systems, Ltd. S71274-05-000 05/10 2