GS4288C09/18/36L 533 MHz300 MHz 144-Ball BGA 32M x 9, 16M x 18, 8M x 36 2.5 V V EXT Commercial Temp 1.8 V V DD 288Mb CIO Low Latency DRAM (LLDRAM) II Industrial Temp 1.5 V or 1.8 V V DDQ Features Introduction Pin- and function-compatible with Micron RLDRAM II The GSI Technology 288Mb Low Latency DRAM 533 MHz DDR operation (1.067Gb/s/pin data rate) (LLDRAM) II is a high speed memory device designed for 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency) high address rate data processing typically found in networking 8M x 36, 16M x 18, and 32M x 9 organizations available and telecommunications applications. The 8-bank architecture 8 internal banks for concurrent operation and maximum and low tRC allows access rates formerly only found in bandwidth SRAMs. Reduced cycle time (15 ns at 533 MHz) Address Multiplexing (Nonmultiplexed address option The Double Data Rate (DDR) I/O interface provides high available) bandwidth data transfers, clocking out two beats of data per SRAM-type interface clock cycle at the I/O balls. Source-synchronous clocking can Programmable Read Latency (RL), row cycle time, and burst be implemented on the host device with the provided free- sequence length running data output clock. Balanced Read and Write Latencies in order to optimize data bus utilization Commands, addresses, and control signals are single data rate Data mask for Write commands signals clocked in by the True differential input clock Differential input clocks (CK, CK) transition, while input data is clocked in on both crossings of Differential input data clocks (DKx, DKx) the input data clock(s). On-chip DLL generates CK edge-aligned data and output data clock signals Read and Write data transfers always in short bursts. The burst Data valid signal (QVLD) length is programmable to 2, 4 or 8 by setting the Mode 32 ms refresh (8K refresh for each bank 64K refresh Register. command must be issued in total each 32 ms) 144-ball BGA package The device is supplied with 2.5 V V and 1.8 V V for the EXT DD HSTL I/O (1.5 V or 1.8 V nominal) core, and 1.5 V or 1.8 V for the HSTL output drivers. 2560 matched impedance outputs 2.5 V V , 1.8 V V , 1.5 V or 1.8 V V I/O EXT DD DDQ Internally generated row addresses facilitate bank-scheduled On-die termination (ODT) R refresh. TT Commerical and Industrial Temperature The device is delivered in an efficent BGA 144-ball package. Commercial (+0 T +95C) C Industrial (40 T +95C) C Rev: 1.03 7/2014 1/62 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS4288C09/18/36L 32M x 9 Mb Ball Assignments144-Ball BGATop View 1 2 3 4 5 6 7 8 9 10 11 12 V V V V V V A TMS TCK REF SS EXT SS SS EXT 3 3 3 V V V V B DQ0 DD DNU DNU SS SS DNU DD 3 3 3 V V V V C DQ1 DNU DNU DNU TT DDQ DDQ TT 1 3 3 V V V D QK0 QK0 A22 DNU DNU SS SS SS 1 3 3 3 V V E DQ2 A20 A21 DNU DNU DDQ DDQ DNU 3 3 3 V V F A5 DQ3 QVLD DNU DNU DNU SS SS V V G A8 A6 A7 A2 A1 A0 DD DD V V V V H B2 A9 A4 A3 SS SS SS SS 2 2 V V V V J B0 CK NF NF DD DD DD DD V V V V K DK DK B1 CK DD DD DD DD V V V V L REF CS A14 A13 SS SS SS SS V V M WE A16 A17 A12 A11 A10 DD DD 3 3 3 N A18 V V DQ4 A19 DNU DNU SS SS DNU 3 3 3 V V P A15 DQ5 DM DNU DNU DDQ DDQ DNU 3 3 3 V V V V R DQ6 SS DNU DNU SS SS DNU SS 3 3 3 V V V V T DQ7 TT DNU DNU DDQ DDQ DNU TT 3 3 3 V V V V U DQ8 DNU DNU DNU DD SS SS DD V V V V V V ZQ TDO TDI REF EXT SS SS EXT Notes: 1. Reserved for future use. This pin may be connected to ground. 2. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND. 3. Do not use. This pin may have parasitic characteristics of an I/O. It may be connected to GND. Rev: 1.03 7/2014 2/62 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see