GS71116ATP/J/U 7, 8, 10, 12 ns SOJ, TSOP, FP-BGA 64K x 16 3.3 V V DD Commercial Temp Center V and V 1Mb Asynchronous SRAM DD SS Industrial Temp Features SOJ 64K x 16-Pin Configuration Fast access time: 7, 8, 10, 12 ns A4 44 A5 1 CMOS low power operation: 145/125/100/85 mA at A3 43 A6 2 minimum cycle time A2 42 A7 3 Single 3.3 V power supply A1 OE 41 4 All inputs and outputs are TTL-compatible Top view A0 UB 40 5 Byte control CE LB 39 6 Fully static operation DQ1 38 DQ16 7 Industrial Temperature Option: 40 to 85C DQ2 37 DQ15 8 Package line up DQ3 36 DQ14 9 DQ4 J: 400 mil, 44-pin SOJ package 35 10 DQ13 44-pin V 34 GJ: RoHS-compliant 400 mil, 44-pin SOJ package 11 DD V SS 33 12 TP: 400 mil, 44-pin TSOP Type II package V V SS DD SOJ 32 13 GP: RoHS-compliant 400 mil, 44-pin TSOP Type II DQ5 DQ12 31 14 DQ6 DQ11 package 30 15 DQ7 DQ10 U: 6 mm x 8 mm Fine Pitch Ball Grid Array package 29 DQ8 DQ9 16 GU: RoHS-compliant 6 mm x 8 mm Fine Pitch Ball Grid 28 WE NC 17 Array package 27 A15 18 A8 A14 26 A9 19 Description A13 25 A10 20 The GS71116A is a high speed CMOS static RAM organized A12 A11 21 24 NC NC as 65,536-words by 16-bits. Static design eliminates the need 22 23 for external clocks or timing strobes. Operating on a single Package J 3.3 V power supply and all inputs and outputs are TTL- compatible. The GS71116A is available in a 6 mm x 8 mm Fine Pitch BGA package, as well as in 400 mil SOJ and 400 Fine Pitch BGA 64K x 16-Bump Configuration mil TSOP Type-II packages . 1 2 3 4 5 6 Pin Descriptions Symbol Description A LB OE A0 A1 A2 NC A0A15 Address input B DQ16 UB A3 A4 CE DQ1 DQ1DQ16 Data input/output C DQ14 DQ15 A5 A6 DQ2 DQ3 CE Chip enable input Lower byte enable input V V D DQ13 NC A7 DQ4 SS DD LB (DQ1 to DQ8) V V E DQ12 NC NC DQ5 DD SS Upper byte enable input UB (DQ9 to DQ16) F DQ11 DQ10 A8 A9 DQ7 DQ6 WE Write enable input G DQ9 NC A10 A11 WE DQ8 OE Output enable input H NC A12 A13 A14 A15 NC V +3.3 V power supply DD V Ground SS 6 mm x 8 mm, 0.75 mm Bump Pitch (Package U) NC No connect Top View Rev: 1.08 6/2006 1/15 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS71116ATP/J/U TSOP-II 64K x 16-Pin Configuration 44 1 A4 A5 43 2 A3 A6 3 42 A2 A7 41 A1 4 OE Top view 40 A0 5 UB 39 6 CE LB 38 7 DQ1 DQ16 37 8 DQ2 DQ15 36 DQ3 9 DQ14 35 DQ4 10 DQ13 44-pin 34 11 V DD V SS 33 12 V V SS DD TSOP II 32 13 DQ5 DQ12 31 14 DQ6 DQ11 30 15 DQ7 DQ10 29 16 DQ8 DQ9 28 17 WE NC 27 18 A15 A8 26 19 A14 A9 25 20 A13 A10 21 24 A12 A11 NC 22 23 NC Package TP Block Diagram A0 Row Memory Array Decoder Address Input Buffer Column Decoder A15 CE WE I/O Buffer Control OE UB DQ1 DQ16 Rev: 1.08 6/2006 2/15 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see