GS71116AGP/U 7, 8, 10, 12 ns TSOP, FP-BGA 64K x 16 3.3 V V DD Commercial Temp Center V and V 1Mb Asynchronous SRAM DD SS Industrial Temp Features Fine Pitch BGA 64K x 16-Bump Configuration Fast access time: 7, 8, 10, 12 ns 1 2 3 4 5 6 CMOS low power operation: 145/125/100/85 mA at minimum cycle time Single 3.3 V power supply LB OE A0 A1 A2 NC A All inputs and outputs are TTL-compatible Byte control B DQ16 UB A3 A4 CE DQ1 Fully static operation Industrial Temperature Option: 40 to 85C C DQ14 DQ15 A5 A6 DQ2 DQ3 Package line up V V D DQ13 NC A7 DQ4 GP: RoHS-compliant 400 mil, 44-pin TSOP Type II SS DD package V V E DQ12 NC NC DQ5 DD SS U: 6 mm x 8 mm Fine Pitch Ball Grid Array package GU: RoHS-compliant 6 mm x 8 mm Fine Pitch Ball Grid F DQ11 DQ10 A8 A9 DQ7 DQ6 Array package G DQ9 NC A10 A11 WE DQ8 Description H NC A12 A13 A14 A15 NC The GS71116A is a high speed CMOS static RAM organized as 65,536-words by 16-bits. Static design eliminates the need for external clocks or timing strobes. Operating on a single 6 mm x 8 mm, 0.75 mm Bump Pitch (Package U) 3.3 V power supply and all inputs and outputs are TTL- Top View compatible. The GS71116A is available in the 6 mm x 8 mm Fine Pitch BGA and 400 mil TSOP Type-II packages. TSOP-II 64K x 16-Pin Configuration 44 1 A4 A5 Pin Descriptions 43 A3 2 A6 42 A2 3 A7 Symbol Description 41 A1 4 OE Top view A0A15 Address input 40 5 A0 UB 39 6 CE LB DQ1DQ16 Data input/output 38 7 DQ1 DQ16 CE Chip enable input 37 DQ2 8 DQ15 36 Lower byte enable input DQ3 9 DQ14 LB 35 DQ4 10 (DQ1 to DQ8) DQ13 44-pin 34 11 V DD V Upper byte enable input SS 33 12 UB V V SS DD (DQ9 to DQ16) TSOP II 32 13 DQ5 DQ12 31 WE Write enable input 14 DQ6 DQ11 30 15 DQ7 DQ10 OE Output enable input 29 16 DQ8 DQ9 V +3.3 V power supply 28 DD 17 WE NC 27 18 A15 A8 V Ground SS 26 19 A14 A9 NC No connect 20 25 A13 A10 21 24 A12 A11 NC 22 23 NC Package TP Rev: 1.10 1/2013 1/13 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS71116AGP/U Block Diagram A0 Row Memory Array Decoder Address Input Buffer Column Decoder A15 CE WE I/O Buffer Control OE UB DQ1 DQ16 Truth Table V Current CE OE WE LB UB DQ1 to DQ8 DQ9 to DQ16 DD H X X X X Not Selected Not Selected ISB1, ISB2 L L Read Read L L H L H Read High Z H L High Z Read L L Write Write IDD L X L L H Write Not Write, High Z H L Not Write, High Z Write L H H X X High Z High Z L X X H H High Z High Z Note: X: H or L Rev: 1.10 1/2013 2/13 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see