GS74104AGP 8, 10, 12 ns TSOP 1M x 4 3.3 V V DD Commercial Temp 4Mb Asynchronous SRAM Center V and V Industrial Temp DD SS Features TSOP-II 1M x 4-Pin Configuration Fast access time: 8, 10, 12 ns CMOS low power operation: 120/95/85 mA at minimum NC 1 44 NC cycle time NC 2 43 NC 42 3 Single 3.3 V power supply NC NC 4 41 All inputs and outputs are TTL-compatible A4 A5 40 Fully static operation A3 5 A6 39 Industrial Temperature Option: 40 to 85C A2 6 A7 38 Package line up A1 7 A8 37 GP:RoHS-compliant 400 mil, 44-pin TSOP Type II A0 8 A9 36 package CE 9 OE 35 DQ1 10 DQ4 44-pin 34 11 V V Description DD SS 12 33 V V SS 400 mil TSOP II DD The GS74104A is a high speed CMOS Static RAM organized 13 32 DQ2 DQ3 as 1,048,576 words by 4 bits. Static design eliminates the need 14 31 WE A10 for external clocks or timing strobes. The GS74104A operates 15 30 A19 A11 on a single 3.3 V power supply and all inputs and outputs are 16 29 A18 A12 TTL-compatible. The GS74104A is available in a RoHS- 17 28 A17 A13 compliant 400 mil TSOP Type-II package. 18 27 A16 A14 26 NC A15 19 25 NC NC 20 NC 21 24 NC Pin Descriptions NC 22 23 NC Symbol Description A0A19 Address input DQ1DQ4 Data input/output CE Chip enable input WE Write enable input OE Output enable input V +3.3 V power supply DD V Ground SS NC No connect Rev: 1.08 1/2013 1/10 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS74104AGP Block Diagram A0 Row Memory Array Decoder Address Input Buffer Column A19 Decoder CE WE I/O Buffer Control OE DQ4 DQ1 Truth Table V Current CE OE WE DQ1 to DQ8 DD H X X Not Selected ISB1, ISB2 L L H Read L X L Write IDD L H H High Z Note: X: H or L Rev: 1.08 1/2013 2/10 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see