GS74116AX-10I GSI Technology

GS74116AGP/X 8, 10, 12 ns TSOP, FP-BGA 256K x 16 3.3 V V DD Commercial Temp Center V and V DD SS 4Mb Asynchronous SRAM Industrial Temp Features FP-BGA 256K x 16 Bump Configuration (Package X) Fast access time: 8, 10, 12 ns 1 2 3 4 5 6 CMOS low power operation: 130/105/95 mA at minimum cycle time Single 3.3 V power supply LB OE A0 A1 A2 NC A All inputs and outputs are TTL-compatible Byte control B DQ16 UB A3 A4 CE DQ1 Fully static operation Industrial Temperature Option: 40 to 85C C DQ14 DQ15 A5 A6 DQ2 DQ3 Package line up D VSS DQ13 A17 A7 DQ4 VDD GP: RoHS-compliant 400 mil, 44-pin TSOP Type II package E VDD DQ12 NC A16 DQ5 VSS X: 6 mm x 10 mm Fine Pitch Ball Grid Array package GX: RoHS-compliant 6 mm x 10 mm Fine Pitch Ball Grid F DQ11 DQ10 A8 A9 DQ7 DQ6 Array package G DQ9 NC A10 A11 WE DQ8 RoHS-compliant TSOP-II, and FP-BGA packages available H NC A12 A13 A14 A15 NC Description The GS74116A is a high speed CMOS Static RAM organized as 262,144 words by 16 bits. Static design eliminates the need 6 x 10 mm Substrate for external clocks or timing strobes. The GS operates on a Top View single 3.3 V power supply and all inputs and outputs are TTL- compatible. The GS74116A is available in a 6 x 10 mm Fine Pitch BGA package and 400 mil TSOP Type-II packages. TSOP-II 256K x 16 Pin Configuration (Package GP) 44 A4 1 A5 43 A3 2 A6 Pin Descriptions 42 3 A2 A7 41 4 A1 OE Top view Symbol Description 40 5 A0 UB 39 CE 6 LB A0A17 Address input 38 DQ1 7 DQ16 DQ1DQ16 Data input/output 37 DQ2 8 DQ15 36 9 DQ3 DQ14 CE Chip enable input 35 10 DQ4 DQ13 Lower byte enable input 44 pin 34 11 V LB DD V SS (DQ1 to DQ8) 33 12 V V SS DD TSOP II 32 Upper byte enable input 13 DQ5 DQ12 UB 31 14 (DQ9 to DQ16) DQ6 DQ11 30 15 DQ7 DQ10 WE Write enable input 29 16 DQ8 DQ9 OE Output enable input 28 17 WE NC 27 18 A15 A8 V +3.3 V power supply DD 26 A14 19 A9 V Ground 25 20 SS A13 A10 21 24 A11 A12 NC No connect 22 23 A16 A17 Rev: 1.10 1/2013 1/13 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS74116AGP/X Block Diagram A0 Row Memory Array Decoder Address Input Buffer Column Decoder A17 CE WE I/O Buffer Control OE UB DQ1 DQ16 Truth Table CE OE WE LB UB DQ1 to DQ8 DQ9 to DQ16 VDD Current H X X X X Not Selected Not Selected ISB1, ISB2 L L Read Read L L H L H Read High Z H L High Z Read L L Write Write IDD L X L L H Write Not Write, High Z H L Not Write, High Z Write L H H X X High Z High Z L X X H H High Z High Z Note: X: H or L Rev: 1.10 1/2013 2/13 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see