Product Information

GS76024AB-10

GS76024AB-10 electronic component of GSI Technology

Datasheet
SRAM 3.3V 256K x 24 6M C Temp

Manufacturer: GSI Technology
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 47.1618 ea
Line Total: USD 47.16

3 - Global Stock
Ships to you between
Wed. 22 May to Fri. 24 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
3 - WHS 1


Ships to you between Wed. 22 May to Fri. 24 May

MOQ : 1
Multiples : 1

Stock Image

GS76024AB-10
GSI Technology

1 : USD 40.204
10 : USD 37.697
21 : USD 36.34
42 : USD 35.443
105 : USD 32.66
252 : USD 32.66
504 : USD 32.2805
1008 : USD 31.395

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Memory Size
Organization
Access Time
Interface Type
Supply Voltage - Max
Supply Voltage - Min
Maximum Operating Temperature
Minimum Operating Temperature
Mounting Style
Package / Case
Supply Current - Max
Memory Type
Series
Type
Brand
Factory Pack Quantity :
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GS76024AB 8, 10, 12 ns BGA 256K x 24 3.3 V V DD Commercial Temp 6Mb Asynchronous SRAM Center V and V Industrial Temp DD SS Features 119-bump Ball Grid Array Package Fast access time: 8, 10, 12 ns CMOS low power operation: 260/210/180 mA at minimum cycle time Single 3.3 V 0.3V power supply All inputs and outputs are TTL-compatible Fully static operation Industrial Temperature Option: 40 to 85C Package B: 14 mm x 22 mm, 119-bump, 1.27 mm pitch BGA GB: RoHS-compliant 119-bump BGA available Description The GS76024A is a high speed CMOS static RAM organized as 262,144 words by 24 bits. Static design eliminates the need for external clocks or timing strobes. Operating on a single 3.3 V power supply and all inputs and outputs are TTL- compatible. The GS76024A is available in a 119-bump BGA package. Block Diagram A0 Row Memory Array Decoder Address Input A17 Column Decoder CE I/O Buffer Control WE OE DQ1 DQ24 Pin Descriptions Symbol Description Symbol Description A0 to A17 Address input DQ1 to DQ24 Data input/output WE Write enable input OE Output enable input CE Chip enable input V V +3.3V power supply Ground DD SS Rev: 1.02a 4/2011 1/12 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS76024AB 119-bump, 1.27 mm Pitch BGA Pad OutTop View (Package B) 1234567 ANCA3 A2 A16 A1 A0 NC BNCA7 A6 CE A5 A4 NC V , V , DD SS CDQ13 NC A17 NC DQ12 NC NC V V V V V DDQ14 DQ11 DD SS SS SS DD V V V EDQ15 NC NC DQ10 DD SS DD V V V V V FDQ16 DQ9 DD SS SS SS DD V V V GDQ17 NC NC DQ8 DD SS DD V V V V V HDQ18 DQ7 DD SS SS SS DD V V V V V V J VSS DD SS DD SS DD DD V V V V V KDQ19 DQ6 DD SS SS SS DD V V V LDQ20 NC NC DQ5 DD SS DD V V V V V MDQ21 DQ4 DD SS SS SS DD V V V NDQ22 NC NC DQ3 DD SS DD V V V V V PDQ23 DQ2 DD SS SS SS DD RDQ24 NC NC NC NC NC DQ1 TNCA11 A10 WE A9 A8 NC UNCA15 A14 OE A13 A12 NC Note: Bumps 3C and 5C are actually NCs but should be wired C3 = V and C5 = V to assure compatibility with future versions. DD SS Rev: 1.02a 4/2011 2/12 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory

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