GS8128218/36(GB/GD)-400/333/250/200 119- & 165-Bump BGA 400 MHz200 MHz 8M x 18, 4M x 36 Commercial Temp 2.5 V or 3.3 V V DD 144Mb S/DCD Sync Burst SRAMs Industrial Temp 2.5 V or 3.3 V I/O Flow Through/Pipeline Reads Features The function of the Data Output register can be controlled by the FT pin for user-configurable flow through or pipeline operation user via the FT mode . Holding the FT mode pin low places the Single/Dual Cycle Deselect selectable RAM in Flow Through mode, causing output data to bypass the IEEE 1149.1 JTAG-compatible Boundary Scan Data Output Register. Holding FT high places the RAM in ZQ mode pin for user-selectable high/low output drive Pipeline mode, activating the rising-edge-triggered Data Output 2.5 V +10%/10% core power supply Register. 3.3 V +10%/10% core power supply 2.5 V or 3.3 V I/O supply SCD and DCD Pipelined Reads LBO pin for Linear or Interleaved Burst mode The GS8128218/36 is a SCD (Single Cycle Deselect) and DCD Internal input resistors on mode pins allow floating mode pins (Dual Cycle Deselect) pipelined synchronous SRAM. DCD Default to SCD x18/x36 Interleaved Pipeline mode SRAMs pipeline disable commands to the same degree as read Byte Write (BW) and/or Global Write (GW) operation commands. SCD SRAMs pipeline deselect commands one stage Internal self-timed write cycle less than read commands. SCD RAMs begin turning off their ZZ pin for automatic power-down outputs immediately after the deselect command has been RoHS-compliant 119-bump and 165-bump BGA packages captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their Functional Description outputs just after the second rising edge of clock. The user may Applications configure this SRAM for either mode of operation using the SCD The GS8128218/36 is a 150,994,944-bit high performance mode input. synchronous SRAM with a 2-bit burst address counter. Although Byte Write and Global Write of a type originally developed for Level 2 Cache applications Byte write operation is performed by using Byte Write enable supporting high performance CPUs, the device now finds (BW) input combined with one or more individual byte write application in synchronous SRAM applications, ranging from signals (Bx). In addition, Global Write (GW) is available for DSP main store to networking chip set support. writing all bytes at one time, regardless of the Byte Write control Controls inputs. Addresses, data I/Os, chip enable (E1), address burst control FLXDrive inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, The ZQ pin allows selection between high drive strength (ZQ low) GW) are synchronous and are controlled by a positive-edge- for multi-drop bus applications and normal drive strength (ZQ triggered clock input (CK). Output enable (G) and power down floating or high) point-to-point applications. See the Output Driver control (ZZ) are asynchronous inputs. Burst cycles can be initiated Characteristics chart for details. with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by Core and Interface Voltages ADV. The burst address counter may be configured to count in The GS8128218/36 operates on a 2.5 V or 3.3 V power supply. either linear or interleave order with the Linear Burst Order (LBO) All input are 3.3 V and 2.5 V compatible. Separate output power input. The Burst function need not be used. New addresses can be (V ) pins are used to decouple output noise from the internal DDQ loaded on every cycle with no degradation of chip performance. circuits and are 3.3 V and 2.5 V compatible. Parameter Synopsis -400 -333 -250 -200 Unit t 2.5 2.5 2.5 3.0 ns KQ 2.5 3.0 4.0 5.0 ns Pipeline tCycle 3-1-1-1 Curr (x18) 610 530 430 360 mA Curr (x32/x36) 690 600 470 400 mA t 4.0 4.5 5.5 6.5 ns KQ 4.0 4.5 5.5 6.5 ns Flow Through tCycle 2-1-1-1 Curr (x18) 430 400 360 295 mA Curr (x32/x36) 470 435 380 330 mA Rev: 1.01a 8/2017 1/36 2015, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8128218/36(GB/GD)-400/333/250/200 119-Bump BGAx36 Common I/OTop View 1 2 3 4 5 6 7 V V A A A ADSP A A A DDQ DDQ B NC A A ADSC A A NC B V C A A A A A NC C DD V V D DQC DQPC ZQ DQPB DQB D SS SS V V E DQC DQC E1 DQB DQB E SS SS F V DQC V G V DQB V F DDQ SS SS DDQ G DQC2 DQC BC ADV BB DQB DQB G V V H DQC DQC GW DQB DQB H SS SS V V V V V J NC NC J DDQ DD DD DD DDQ V V K DQD DQD CK DQA DQA K SS SS L DQD DQD BD SCD BA DQA DQA L V V V V M DQD BW DQA M DDQ SS SS DDQ V V N DQD DQD A1 DQA DQA N SS SS V P DQD DQPD A0 V DQPA DQA P SS SS V R NC A LBO FT A NC R DD T NC A A A A A ZZ T V V U TMS TDI TCK TDO NC U DDQ DDQ 2 7 x 17 Bump BGA14 x 22 mm Body1.27 mm Bump Pitch Rev: 1.01a 8/2017 2/36 2015, GSI Technology Specifications cited are subject to change without notice. For latest documentation see