GS81284Z18/36B-250/200/167 119-Bump BGA 250 MHz167 MHz 144Mb Pipelined and Flow Through Commercial Temp 2.5 V or 3.3 V V DD Synchronous NBT SRAM Industrial Temp 2.5 V or 3.3 V I/O Features Because it is a synchronous device, address, data inputs, and NBT (No Bus Turn Around) functionality allows zero wait read/write control inputs are captured on the rising edge of the Read-Write-Read bus utilization fully pin-compatible with input clock. Burst order control (LBO) must be tied to a power both pipelined and flow through NtRAM, NoBL and rail for proper operation. Asynchronous inputs include the ZBT SRAMs Sleep mode enable (ZZ) and Output Enable. Output Enable can 2.5 V or 3.3 V +10%/10% core power supply be used to override the synchronous control of the output 2.5 V or 3.3 V I/O supply drivers and turn the RAM s output drivers off at any time. User-configurable Pipeline and Flow Through mode Write cycles are internally self-timed and initiated by the rising ZQ mode pin for user-selectable high/low output drive edge of the clock input. This feature eliminates complex off- IEEE 1149.1 JTAG-compatible Boundary Scan chip write pulse generation required by asynchronous SRAMs LBO pin for Linear or Interleave Burst mode and simplifies input signal timing. Pin-compatible with 8Mb, 16Mb, 36Mb and 72Mb devices Byte write operation (9-bit Bytes) The GS81284Z18/36 may be configured by the user to operate 3 chip enable signals for easy depth expansion in Pipeline or Flow Through mode. Operating as a pipelined ZZ Pin for automatic power-down synchronous device, in addition to the rising-edge-triggered JEDEC-standard 119-bump BGA package registers that capture input signals, the device incorporates a RoHS-compliant 119-bump BGA packages available rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered Functional Description output register during the access cycle and then released to the The GS81284Z18/36 is a 144Mbit Synchronous Static SRAM. output drivers at the next rising edge of clock. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL or other The GS81284Z18/36 is implemented with GSI s high pipelined read/double late write or flow through read/single performance CMOS technology and is available in a JEDEC- late write SRAMs, allow utilization of all available bus standard 119-bump BGA package. bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Parameter Synopsis -250 -200 -167 Unit t (x18/x36) 2.5 3.0 3.4 ns KQ 4.0 5.0 6.0 ns tCycle Pipeline 3-1-1-1 Curr (x18) 480 420 385 mA Curr (x36) 550 480 430 mA t 6.5 7.5 8.0 ns KQ 6.5 7.5 8.0 ns Flow Through tCycle 2-1-1-1 Curr (x18) 370 340 330 mA Curr (x36) 405 370 360 mA Rev: 1.02 7/2010 1/29 2007, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS81284Z18/36B-250/200/167 GS81284Z36B Pad Out119-Bump BGATop View 1 2 3 4 5 6 7 A V A A A A A V A DDQ DDQ B NC E2 A ADV A E3 NC B C NC A A V A A NC C DD D DQC DQPC V ZQ V DQPB DQB D SS SS E DQC DQC V E1 V DQB DQB E SS SS F V DQC V G V DQB V F DDQ SS SS DDQ G DQC DQC BC A BB DQB DQB G H DQC DQC V W V DQB DQB H SS SS J V V NC V NC V V J DDQ DD DD DD DDQ K DQD DQD V CK V DQA DQA K SS SS L DQD DQD BD NC BA DQA DQA L M V DQD V CKE V DQA V M DDQ SS SS DDQ N DQD DQD V A1 V DQA DQA N SS SS P DQD DQPD V A0 V DQPA DQA P SS SS R A A LBO V FT A NC R DD T NC A A A A A ZZ T U V TMS TDI TCK TDO NC V U DDQ DDQ 2 7 x 17 Bump BGA14 x 22 mm Body1.27 mm Bump Pitch Rev: 1.02 7/2010 2/29 2007, GSI Technology Specifications cited are subject to change without notice. For latest documentation see