GS81284Z18/36B-xxxV
119-Bump BGA 200 MHz167 MHz
144Mb Pipelined and Flow Through
Commercial Temp 1.8 V or 2.5 V V
DD
Synchronous NBT SRAM
Industrial Temp
1.8 V or 2.5 V I/O
Because it is a synchronous device, address, data inputs, and
Features
read/write control inputs are captured on the rising edge of the
NBT (No Bus Turn Around) functionality allows zero wait
input clock. Burst order control (LBO) must be tied to a power
Read-Write-Read bus utilization; fully pin-compatible with
rail for proper operation. Asynchronous inputs include the
both pipelined and flow through NtRAM, NoBL and
Sleep mode enable (ZZ) and Output Enable. Output Enable can
ZBT SRAMs
be used to override the synchronous control of the output
1.8 V 2.5 V core power supply
drivers and turn the RAM's output drivers off at any time.
1.8 V or 2.5 V I/O supply
Write cycles are internally self-timed and initiated by the rising
User-configurable Pipeline and Flow Through mode
edge of the clock input. This feature eliminates complex off-
ZQ mode pin for user-selectable high/low output drive
chip write pulse generation required by asynchronous SRAMs
IEEE 1149.1 JTAG-compatible Boundary Scan
and simplifies input signal timing.
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 8Mb, 36Mb, and 72Mb devices
The GS81284Z18/36-xxxV may be configured by the user to
Byte write operation (9-bit Bytes)
operate in Pipeline or Flow Through mode. Operating as a
3 chip enable signals for easy depth expansion
pipelined synchronous device, in addition to the rising-edge-
ZZ Pin for automatic power-down
triggered registers that capture input signals, the device
JEDEC-standard 119-BGA package
incorporates a rising edge triggered output register. For read
RoHS-compliant 119-BGA packages available
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
Functional Description
then released to the output drivers at the next rising edge of
The GS81284Z18/36(B)-xxxV is a 144Mbit Synchronous
clock.
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/ The GS81284Z18/36-xxxV is implemented with GSI's high
single late write SRAMs, allow utilization of all available bus performance CMOS technology and is available in a JEDEC-
bandwidth by eliminating the need to insert deselect cycles standard 119-bump p BGA package.
when the device is switched from read to write cycles.
Parameter Synopsis
-200 -167 Unit
t 3.0 3.4 ns
KQ
5.0 6.0 ns
tCycle
Pipeline
3-1-1-1
Curr (x18) 420 385 mA
Curr (x36) 480 430 mA
t
7.5 8.0 ns
KQ
7.5 8.0 ns
Flow Through tCycle
2-1-1-1
Curr (x18) 340 330 mA
Curr (x36) 370 360 mA
Rev: 1.02 7/2010 1/28 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see GS81284Z18/36B-xxxV
GS81284Z36B-xxxV Pad Out119-Bump BGATop View
1 2 3 4 5 6 7
A V A A A A A V A
DDQ DDQ
B NC E2 A ADV A E3 NC B
C NC A A V A A NC C
DD
D DQC DQPC V ZQ V DQPB DQB D
SS SS
E DQC DQC V E1 V DQB DQB E
SS SS
F V DQC V G V DQB V F
DDQ SS SS DDQ
G DQC DQC BC A BB DQB DQB G
H DQC DQC V W V DQB DQB H
SS SS
J V V NC V NC V V J
DDQ DD DD DD DDQ
K DQD DQD V CK V DQA DQA K
SS SS
L DQD DQD BD NC BA DQA DQA L
M V DQD V CKE V DQA V M
DDQ SS SS DDQ
N DQD DQD V A1 V DQA DQA N
SS SS
P DQD DQPD V A0 V DQPA DQA P
SS SS
R A A LBO V FT A NC R
DD
T NC A A A A A ZZ T
U V TMS TDI TCK TDO NC V U
DDQ DDQ
2
7 x 17 Bump BGA14 x 22 mm Body1.27 mm Bump Pitch
Rev: 1.02 7/2010 2/28 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see