GS81302DT20/38AGD-633/550/500/450 633 MHz450 MHz 165-Bump BGA 144Mb SigmaQuad-II+ 1.8 V V Commercial Temp DD Burst of 4 SRAM Industrial Temp 1.8 V or 1.5 V I/O Features Clocking and Addressing Schemes 2.5 Clock Latency The GS81302DT20/38AGD SigmaQuad-II+ SRAMs are Simultaneous Read and Write SigmaQuad Interface synchronous devices. They employ two input register clock JEDEC-standard pinout and package inputs, K and K. K and K are independent single-ended clock Dual Double Data Rate interface inputs, not differential inputs to a single differential clock input Byte Write controls sampled at data-in time buffer. Burst of 4 Read and Write Dual-Range On-Die Termination (ODT) on Data (D), Byte Each internal read and write operation in a SigmaQuad-II+ B4 Write (BW), and Clock (K, K) intputs RAM is four times wider than the device I/O bus. An input 1.8 V +100/100 mV core power supply data bus de-multiplexer is used to accumulate incoming data 1.5 V or 1.8 V HSTL Interface before it is simultaneously written to the memory array. An Pipelined read operation output data multiplexer is used to capture the data produced Fully coherent read and write pipelines from a single memory array read and then route it to the ZQ pin for programmable output drive strength appropriate output drivers as needed. Therefore the address Data Valid Pin (QVLD) Support field of a SigmaQuad-II+ B4 RAM is always two address pins IEEE 1149.1 JTAG-compliant Boundary Scan less than the advertised index depth (e.g., the 8M x 18 has a RoHS-compliant 165-bump BGA package 2M addressable index). SigmaQuad Family Overview The GS81302DT20/38AGD are built in compliance with the SigmaQuad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. The GS81302DT20/38AGD SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Parameter Synopsis -633 -550 -500 -450 tKHKH 1.58 ns 1.81 ns 2.0 ns 2.2 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns Rev: 1.01 2/2018 1/26 2017, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS81302DT20/38AGD-633/550/500/450 4M x 36 SigmaQuad-II+ SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 NC/SA A CQ SA W BW2 K BW1 R SA SA CQ (288Mb) B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8 C D27 Q28 D19 V SA NC SA V D16 Q7 D8 SS SS D D28 D20 Q19 V V V V V Q16 D15 D7 SS SS SS SS SS E Q29 D29 Q20 V V V V V Q15 D6 Q6 DDQ SS SS SS DDQ F Q30 Q21 D21 V V V V V D14 Q14 Q5 DDQ DD SS DD DDQ G D30 D22 Q22 V V V V V Q13 D13 D5 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J D31 Q31 D23 V V V V V D12 Q4 D4 DDQ DD SS DD DDQ K Q32 D32 Q23 V V V V V Q12 D3 Q3 DDQ DD SS DD DDQ L Q33 Q24 D24 V V V V V D11 Q11 Q2 DDQ SS SS SS DDQ M D33 Q34 D25 V V V V V D10 Q1 D2 SS SS SS SS SS N D34 D26 Q25 V SA SA SA V Q10 D9 D1 SS SS P Q35 D35 Q26 SA SA QVLD SA SA Q9 D0 Q0 R TDO TCK SA SA SA ODT SA SA SA TMS TDI 2 11 x 15 Bump BGA13 x 15 mm Body1 mm Bump Pitch Note: BW0 controls writes to D0:D8 BW1 controls writes to D9:D17 BW2 controls writes to D18:D26 BW3 controls writes to D27:D35 Rev: 1.01 2/2018 2/26 2017, GSI Technology Specifications cited are subject to change without notice. For latest documentation see