GS81314LD19/37GK-933/800 Up to 933 MHz 260-Pin BGA 144Mb SigmaQuad-IVe 1.25V ~ 1.3V V Com & Ind Temp DD Burst of 4 Single-Bank ECCRAM HSTL I/O 1.2V ~ 1.3V V DDQ Features Clocking and Addressing Schemes 4Mb x 36 and 8Mb x 18 organizations available The GS81314LD19/37GK SigmaQuad-IVe ECCRAMs are synchronous devices. They employ three pairs of positive and Organized as a single logical memory bank negative input clocks one pair of master clocks, CK and CK, 933 MHz maximum operating frequency and two pairs of write data clocks, KD 1:0 and KD 1:0 . All 933 MT/s peak transaction rate (in millions per second) six input clocks are single-ended that is, each is received by a 134 Gb/s peak data bandwidth (in x36 devices) dedicated input buffer. Separate I/O DDR Data Buses Non-multiplexed SDR Address Bus CK and CK are used to latch address and control inputs, and to One operation - Read or Write - per clock cycle control all output timing. KD 1:0 and KD 1:0 are used solely No address/bank restrictions on Read and Write ops to latch data inputs. Burst of 4 Read and Write operations 5 cycle Read Latency Each internal read and write operation in a SigmaQuad-IVe B4 On-chip ECC with virtually zero SER ECCRAM is four times wider than the device I/O bus. An Loopback signal timing training capability input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. 1.25V ~ 1.3V nominal core voltage An output data multiplexer is used to capture the data produced 1.2V ~ 1.3V HSTL I/O interface from a single memory array read and then route it to the Configuration registers appropriate output drivers as needed. Therefore, the address Configurable ODT (on-die termination) field of a SigmaQuad-IVe B4 ECCRAM is always two address ZQ pin for programmable driver impedance pins less than the advertised index depth (e.g. the 8M x 18 has ZT pin for programmable ODT impedance 2M addressable index). IEEE 1149.1 JTAG-compliant Boundary Scan 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS- On-Chip Error Correction Code compliant BGA package GSI s ECCRAMs implement an ECC algorithm that detects and corrects all single-bit memory errors, including those SigmaQuad-IVe Family Overview induced by SER events such as cosmic rays, alpha particles, SigmaQuad-IVe ECCRAMs are the Separate I/O half of the etc. The resulting Soft Error Rate of these devices is SigmaQuad-IVe/SigmaDDR-IVe family of high performance anticipated to be <0.002 FITs/Mb a 5-order-of-magnitude ECCRAMs. Although similar to GSI s third generation of improvement over comparable SRAMs with no on-chip ECC, networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe which typically have an SER of 200 FITs/Mb or more. family), these fourth generation devices offer several new features that help enable significantly higher performance. All quoted SER values are at sea level in New York City. Parameter Synopsis V Speed Grade Max Operating Frequency Read Latency DD -933 933 MHz 5 cycles 1.25V to 1.35V -800 800 MHz 5 cycles 1.2V to 1.35V Rev: 1.04 7/2018 1/39 2015, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS81314LD19/37GK-933/800 8M x 18 Pinout (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 NC MCH V V V V MRW V V V V ZQ PZT1 A DD DDQ DD DDQ DDQ DD DDQ DD (RSVD) (CFG) MCH NC MCH V NU V NU V V B MCL PZT0 D0 Q0 SS O SS I SS SS (B4M) (RSVD) (SIOM) V V V V V V NU V NU Q17 D17 SA13 SA14 C DDQ DDQ SS DD SS DDQ I DDQ O NC V NU V NU V V V V D SA19 SA20 D1 Q1 SS O SS I DDQ DDQ SS SS (288 Mb) Q16 V D16 V V SA11 V SA12 V V NU V NU E DDQ DD SS SS SS DD I DDQ O V NU V NU V V V V V SA17 SA18 D2 Q2 F SS O SS I DD DDQ DD SS SS NU NU V V NU NU G Q15 D15 SA9 MZT1 SA10 D3 Q3 O I SS SS I O V V V V V NU V NU Q14 D14 SA15 W SA16 H DDQ DDQ DDQ DDQ DDQ I DDQ O V NU V NU V V V V V J SA7 SA8 D4 Q4 SS O SS I SS SS SS SS SS CQ1 V V V KD1 V CK V KD0 V V V CQ0 K DDQ REF DD DD DD DD REF DDQ V V V V V V CQ1 QVLD1 KD1 CK KD0 QVLD0 CQ0 L SS ss DDQ DDQ SS SS V V V V V NU V NU V M Q13 D13 SA5 SA6 SS SS SS SS SS I SS O SS NU V NU V V V V V PLL R MCL D5 Q5 N O DDQ I DDQ DDQ DDQ DDQ DDQ NU NU V V NU NU P Q12 D12 SA3 MZT0 SA4 D6 Q6 O I SS SS I O V Q11 V D11 MCH V V V RST NU V NU V R SS SS DD DDQ DD I SS O SS NU V NU V V V V V V SA1 SA2 D7 Q7 T O DDQ I DD SS SS SS DD DDQ NC NC NC V V V V NU V NU V U Q10 D10 SS SS DDQ DDQ I SS O SS (576 Mb) (RSVD) (1152 Mb) SA21 NU I NU V NU V V V V V V D8 Q8 V O DDQ I DDQ SS DD SS DDQ DDQ (x18) (B2) V V NU V NU V W Q9 D9 TCK MCL RCS MCL TMS SS SS I SS O SS NC V V V V TDO ZT MCL TDI V V V V Y DD DDQ DD DDQ DDQ DD DDQ DD (RSVD) Notes: 1. Pins 5B, 6W, 8W, 8Y, and 9N must be tied Low in this device. 2. Pin 5R must be tied High in this device. 3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration. 4. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration. 5. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration. 6. Pin 6V is defined as address pin SA for x18 devices. It is used in this device. 7. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low. 8. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device. 9. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device. 10. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device. Rev: 1.04 7/2018 2/39 2015, GSI Technology Specifications cited are subject to change without notice. For latest documentation see