GS816118D(GT/D)/GS816132D(D)/GS816136D(GT/D) 400 MHz150 MHz 100-Pin TQFP & 165-Bump BGA 1M x 18, 512K x 32, 512K x 36 2.5 V or 3.3 V V Commercial Temp DD 2.5 V or 3.3 V I/O Industrial Temp 18Mb Sync Burst SRAMs Linear Burst Order (LBO) input. The Burst function need not Features be used. New addresses can be loaded on every cycle with no FT pin for user-configurable flow through or pipeline degradation of chip performance. operation Single Cycle Deselect (SCD) operation Flow Through/Pipeline Reads IEEE 1149.1 JTAG-compatible Boundary Scan The function of the Data Output register can be controlled by 2.5 V or 3.3 V +10%/10% core power supply the user via the FT mode pin (Pin 14). Holding the FT mode 2.5 V or 3.3 V I/O supply pin low places the RAM in Flow Through mode, causing LBO pin for Linear or Interleaved Burst mode output data to bypass the Data Output Register. Holding FT Internal input resistors on mode pins allow floating mode pins high places the RAM in Pipeline mode, activating the rising- Byte Write (BW) and/or Global Write (GW) operation edge-triggered Data Output Register. Internal self-timed write cycle SCD Pipelined Reads Automatic power-down for portable applications The GS816118D(GT/D)/GS816132D(D)/GS816136D(GT/D) JEDEC-standard 165-bump BGA package (Single Cycle Deselect) pipelined synchronous SRAM. DCD RoHS-compliant 100-pin TQFP and 165-bump BGA packages (Dual Cycle Deselect) versions are also available. SCD available SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs Functional Description immediately after the deselect command has been captured in Applications the input registers. The GS816118D(GT/D)/GS816132D(D)/GS816136D(GT/D) is Byte Write and Global Write an 18,874,368-bit high performance synchronous SRAM with Byte write operation is performed by using Byte Write enable a 2-bit burst address counter. Although of a type originally (BW) input combined with one or more individual byte write developed for Level 2 Cache applications supporting high signals (Bx). In addition, Global Write (GW) is available for performance CPUs, the device now finds application in writing all bytes at one time, regardless of the Byte Write synchronous SRAM applications, ranging from DSP main control inputs. store to networking chip set support. Sleep Mode Controls Low power (Sleep mode) is attained through the assertion Addresses, data I/Os, chip enable (E1), address burst control (High) of the ZZ signal, or by stopping the clock (CK). inputs (ADSP, ADSC, ADV) and write control inputs (Bx, Memory data is retained during Sleep mode. BW, GW) are synchronous and are controlled by a positive- Core and Interface Voltages edge-triggered clock input (CK). Output enable (G) and power The GS816118D(GT/D)/GS816132D(D)/GS816136D(GT/D) down control (ZZ) are asynchronous inputs. Burst cycles can operates on a 3.3 V or 2.5 V power supply. All input are 3.3 V be initiated with either ADSP or ADSC inputs. In Burst mode, and 2.5 V compatible. Separate output power (V ) pins are subsequent burst addresses are generated internally and are DDQ controlled by ADV. The burst address counter may be used to decouple output noise from the internal circuits and are configured to count in either linear or interleave order with the 3.3 V and 2.5 V compatible. Parameter Synopsis -400 -375 -333 -250 -200 -150 Unit t 2.5 2.5 2.5 2.5 3.0 3.8 ns KQ 2.5 2.66 3.3 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 370 350 310 250 210 185 mA Curr (x32/x36) 430 410 365 290 240 200 mA t 4.0 4.2 4.5 5.5 6.5 7.5 ns KQ Flow 4.0 4.2 4.5 5.5 6.5 7.5 ns tCycle Through Curr (x18) 275 265 255 220 205 190 mA 2-1-1-1 Curr (x32/x36) 315 300 285 250 225 205 mA Rev: 1.03b 9/2013 1/37 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS816118D(GT/D)/GS816132D(D)/GS816136D(GT/D) GS816118D 100-Pin TQFP Pinout 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 1M X 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 FT 67 SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.03b 9/2013 2/37 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see