GS8161Z18D(GT/D)/GS8161Z32D(D)/GS8161Z36D(GT/D) 400 MHz150 MHz 100-Pin TQFP & 165-Bump BGA 18Mb Pipelined and Flow Through 1.8 V, 2.5 V, or 3.3 V V DD Commercial Temp 1.8 V, 2.5 V, or 3.3 V I/O Industrial Temp Synchronous NBT SRAM Because it is a synchronous device, address, data inputs, and Features read/ write control inputs are captured on the rising edge of the User-configurable Pipeline and Flow Through mode input clock. Burst order control (LBO) must be tied to a power NBT (No Bus Turn Around) functionality allows zero wait rail for proper operation. Asynchronous inputs include the read-write-read bus utilization Sleep mode enable, ZZ and Output Enable. Output Enable can Fully pin-compatible with both pipelined and flow through be used to override the synchronous control of the output NtRAM, NoBL and ZBT SRAMs drivers and turn the RAM s output drivers off at any time. IEEE 1149.1 JTAG-compatible Boundary Scan Write cycles are internally self-timed and initiated by the rising 1.8 V, 2.5 V, or 3.3 V +10%/10% core power supply edge of the clock input. This feature eliminates complex off- LBO pin for Linear or Interleave Burst mode chip write pulse generation required by asynchronous SRAMs Pin-compatible with 2Mb, 4Mb, 8Mb, 36Mb, 72Mb and and simplifies input signal timing. 144Mb devices Byte write operation (9-bit Bytes) The GS8161Z18D(GT/D)/GS8161Z32D(D)/ 3 chip enable signals for easy depth expansion GS8161Z36D(GT/D) may be configured by the user to operate ZZ pin for automatic power-down in Pipeline or Flow Through mode. Operating as a pipelined JEDEC-standard 165-bump BGA package synchronous device, in addition to the rising-edge-triggered RoHS-compliant 100-pin TQFP and 165-bump BGA registers that capture input signals, the device incorporates a packages available rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered Functional Description output register during the access cycle and then released to the The GS8161Z18D(GT/D)/GS8161Z32D(D)/ output drivers at the next rising edge of clock. GS8161Z36D(GT/D) is an 18Mbit Synchronous Static SRAM. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL or other The GS8161Z18D(GT/D)/GS8161Z32D(D)/ pipelined read/double late write or flow through read/single GS8161Z36D(GT/D) is implemented with GSI s high late write SRAMs, allow utilization of all available bus performance CMOS technology and is available in JEDEC- bandwidth by eliminating the need to insert deselect cycles standard 165-bump BGA package. when the device is switched from read to write cycles. Parameter Synopsis -400 -375 -333 -250 -200 -150 Unit t 2.5 2.5 2.5 2.5 3.0 3.8 ns KQ 2.5 2.66 3.3 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 370 350 310 250 210 185 mA Curr (x32/x36) 430 410 365 290 240 200 mA t 4.0 4.2 4.5 5.5 6.5 7.5 ns KQ Flow 4.0 4.2 4.5 5.5 6.5 7.5 ns tCycle Through Curr (x18) 275 265 255 220 205 190 mA 2-1-1-1 Curr (x32/x36) 315 300 285 250 225 205 mA Rev: 1.03b 9/2013 1/40 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8161Z18D(GT/D)/GS8161Z32D(D)/GS8161Z36D(GT/D) GS8161Z18DT Pinout (Package T) 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 1M x 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA5 13 DQB 68 V 14 FT 67 SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.03b 9/2013 2/40 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see