GS816218/36D(B/D)-xxxV 119 & 165 BGA 333 MHz150 MHz 1M x 18, 512K x 36 Commercial Temp 1.8 V or 2.5 V V DD 18Mb S/DCD Sync Burst SRAMs Industrial Temp 1.8 V or 2.5 V I/O Flow Through/Pipeline Reads Features The function of the Data Output register can be controlled by the FT pin for user-configurable flow through or pipeline operation user via the FT mode . Holding the FT mode pin low places the Single/Dual Cycle Deselect selectable RAM in Flow Through mode, causing output data to bypass the IEEE 1149.1 JTAG-compatible Boundary Scan Data Output Register. Holding FT high places the RAM in ZQ mode pin for user-selectable high/low output drive Pipeline mode, activating the rising-edge-triggered Data Output 1.8 V or 2.5 V core power supply Register. 1.8 V or 2.5 V I/O supply LBO pin for Linear or Interleaved Burst mode SCD and DCD Pipelined Reads Internal input resistors on mode pins allow floating mode pins The GS816218/36D-xxxV is a SCD (Single Cycle Deselect) and Default to SCD x18/x36 Interleaved Pipeline mode DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD Byte Write (BW) and/or Global Write (GW) operation SRAMs pipeline disable commands to the same degree as read Internal self-timed write cycle commands. SCD SRAMs pipeline deselect commands one stage Automatic power-down for portable applications less than read commands. SCD RAMs begin turning off their JEDEC-standard 119- and 165-bump BGA packages outputs immediately after the deselect command has been RoHS-compliant packages available captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their Functional Description outputs just after the second rising edge of clock. The user may Applications configure this SRAM for either mode of operation using the SCD The GS816218/36D-xxxV is an 18,874,368-bit high performance mode input. synchronous SRAM with a 2-bit burst address counter. Although Byte Write and Global Write of a type originally developed for Level 2 Cache applications Byte write operation is performed by using Byte Write enable supporting high performance CPUs, the device now finds (BW) input combined with one or more individual byte write application in synchronous SRAM applications, ranging from signals (Bx). In addition, Global Write (GW) is available for DSP main store to networking chip set support. writing all bytes at one time, regardless of the Byte Write control Controls inputs. Addresses, data I/Os, chip enable (E1), address burst control FLXDrive inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, The ZQ pin allows selection between high drive strength (ZQ low) GW) are synchronous and are controlled by a positive-edge- for multi-drop bus applications and normal drive strength (ZQ triggered clock input (CK). Output enable (G) and power down floating or high) point-to-point applications. See the Output Driver control (ZZ) are asynchronous inputs. Burst cycles can be initiated Characteristics chart for details. with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by Core and Interface Voltages ADV. The burst address counter may be configured to count in The GS816218/36D-xxxV operates on a 1.8 V or 2.5 V power either linear or interleave order with the Linear Burst Order (LBO) supply. All inputs are 1.8 V or 2.5 V compatible. Separate output input. The Burst function need not be used. New addresses can be power (V ) pins are used to decouple output noise from the DDQ loaded on every cycle with no degradation of chip performance. internal circuits and are 1.8 V or 2.5 V compatible. Parameter Synopsis -333 -250 -200 -150 Unit t 3.0 3.0 3.0 3.8 ns KQ 3.0 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 305 245 205 175 mA Curr (x36) 360 285 235 195 mA t 5.0 5.5 6.5 7.5 ns KQ Flow 5.0 5.5 6.5 7.5 ns tCycle Through Curr (x18) 235 215 205 190 mA 2-1-1-1 Curr (x36) 265 245 225 205 mA Rev: 1.03b 9/2013 1/36 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS816218/36D(B/D)-xxxV 165-Bump BGAx18 Common I/OTop View (Package D) 1 2 3 4 5 6 7 8 9 10 11 A NC A E1 BB NC E3 BW ADSC ADV A A A B NC A E2 NC BA CK GW G ADSP A NC B C NC NC V V V V V V V NC DQPA C DDQ SS SS SS SS SS DDQ D NC DQB V V V V V V V NC DQA D DDQ DD SS SS SS DD DDQ E NC DQB V V V V V V V NC DQA E DDQ DD SS SS SS DD DDQ F NC DQB V V V V V V V NC DQA F DDQ DD SS SS SS DD DDQ G NC DQB V V V V V V V NC DQA G DDQ DD SS SS SS DD DDQ H FT MCL NC V V V V V NC ZQ ZZ H DD SS SS SS DD J DQB NC V V V V V V V DQA NC J DDQ DD SS SS SS DD DDQ K DQB NC V V V V V V V DQA NC K DDQ DD SS SS SS DD DDQ L DQB NC V V V V V V V DQA NC L DDQ DD SS SS SS DD DDQ M DQB NC V V V V V V V DQA NC M DDQ DD SS SS SS DD DDQ N DQPB SCD V V NC A NC V V NC NC N DDQ SS SS DDQ P NC NC A A TDI A1 TDO A A A A P R LBO NC A A TMS A0 TCK A A A A R 11 x 15 Bump BGA13 mm x 15 mm Body1.0 mm Bump Pitch Rev: 1.03b 9/2013 2/36 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see