GS816273CC-333/300/250 333 MHz250 MHz 209-Bump BGA 256K x 72 3.3 V or 2.5 V V DD Commercial Temp 18Mb S/DCD Sync Burst SRAMs 3.3 V or 2.5 V I/O Industrial Temp with the Linear Burst Order (LBO) input. The Burst function need not Features be used. New addresses can be loaded on every cycle with no Single/Dual Cycle Deselect selectable degradation of chip performance. IEEE 1149.1 JTAG-compatible Boundary Scan ZQ mode pin for user-selectable high/low output drive SCD and DCD Pipelined Reads 3.3 V or 2.5 V core power supply The GS816273CC is an SCD (Single Cycle Deselect) and DCD (Dual 3.3 V or 2.5 V I/O supply Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs LBO pin for Linear or Interleaved Burst mode pipeline disable commands to the same degree as read commands. Internal input resistors on mode pins allow floating mode pins SCD SRAMs pipeline deselect commands one stage less than read Default to SCD x18/x36 Interleaved Pipeline mode commands. SCD RAMs begin turning off their outputs immediately Byte Write (BW) and/or Global Write (GW) operation after the deselect command has been captured in the input registers. Internal self-timed write cycle DCD RAMs hold the deselect command for one full cycle and then Automatic power-down for portable applications begin turning off their outputs just after the second rising edge of JEDEC-standard 209-bump BGA package clock. The user may configure this SRAM for either mode of RoHS-compliant 209-bump BGA package available operation using the SCD mode input. Byte Write and Global Write Functional Description Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). Applications In addition, Global Write (GW) is available for writing all bytes at one The GS816273CC is an 18,874,368-bit high performance time, regardless of the Byte Write control inputs. synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting FLXDrive high performance CPUs, the device now finds application in The ZQ pin allows selection between high drive strength (ZQ low) for synchronous SRAM applications, ranging from DSP main store to multi-drop bus applications and normal drive strength (ZQ floating or networking chip set support. high) point-to-point applications. See the Output Driver Characteristics chart for details. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs Sleep Mode (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are Low power (Sleep mode) is attained through the assertion (High) of synchronous and are controlled by a positive-edge-triggered clock the ZZ signal, or by stopping the clock (CK). Memory data is retained input (CK). Output enable (G) and power down control (ZZ) are during Sleep mode. asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are Core and Interface Voltages The GS816273CC operates on a 3.3 V or 2.5 V power supply. All generated internally and are controlled by ADV. The burst address inputs are 3.3 V or 2.5 V compatible. Separate output power (V ) DDQ counter may be configured to count in either linear or interleave order pins are used to decouple output noise from the internal circuits and are 3.3 V or 2.5 V compatible. Parameter Synopsis -333 -300 -250 Unit t 2.3 2.3 2.5 ns KQ Pipeline 3.0 3.3 4.0 ns tCycle 3-1-1-1 Curr 545 495 425 mA Rev: 1.03 3/2008 1/28 2005, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS816273CC-333/300/250 GS816273C Pad Out209-Bump BGATop View (Package C) 1 2 3 4 5 6 7 8 9 10 11 A DQG DQG A E2 ADSP ADSC ADV E3 A DQB DQB B DQG DQG BC BG NC B A BB BF DQB DQB C DQG DQG BH BD NC E1 NC BE BA DQB DQB D DQG DQG V NC NC G GW NC V DQB DQB SS SS E DQPG DQPC V V V V V V V DQPF DQPB DDQ DDQ DD DD DD DDQ DDQ F DQC DQC V V V ZQ V V V DQF DQF SS SS SS SS SS SS G DQC DQC V V V MCH V V V DQF DQF DDQ DDQ DD DD DDQ DDQ H DQC DQC V V V MCL V V V DQF DQF SS SS SS SS SS SS J DQC DQC V V V MCL V V V DQF DQF DDQ DDQ DD DD DDQ DDQ K NC NC CK NC V MCL V NC NC NC NC SS SS L DQH DQH V V V V /DNU V V V DQA DQA DDQ DDQ DD DDQ DD DDQ DDQ M DQH DQH V V V MCL V V V DQA DQA SS SS SS SS SS SS N DQH DQH V V V SCD V V V DQA DQA DDQ DDQ DD DD DDQ DDQ P DQH DQH V V V ZZ V V V DQA DQA SS SS SS SS SS SS R DQPD DQPH V V V V V V V DQPA DQPE DDQ DDQ DD DD DD DDQ DDQ T DQD DQD V NC NC LBO NC NC V DQE DQE SS SS U DQD DQD NC A A A A A NC DQE DQE V DQD DQD A A A A1 A A A DQE DQE W DQD DQD TMS TDI A A0 A TDO TCK DQE DQE Rev 10 2 11 x 19 Bump BGA14 x 22 mm Body1 mm Bump Pitch Rev: 1.03 3/2008 2/28 2005, GSI Technology Specifications cited are subject to change without notice. For latest documentation see