GS8162Z18/36D(B/D)-xxxV 333 MHz150 MHz 119 & 165 BGA 18Mb Pipelined and Flow Through 1.8 V or 2.5 V V Commercial Temp DD Synchronous NBT SRAM Industrial Temp 1.8 V or 2.5 V I/O Because it is a synchronous device, address, data inputs, and Features read/write control inputs are captured on the rising edge of the NBT (No Bus Turn Around) functionality allows zero wait input clock. Burst order control (LBO) must be tied to a power Read-Write-Read bus utilization fully pin-compatible with rail for proper operation. Asynchronous inputs include the both pipelined and flow through NtRAM, NoBL and Sleep mode enable (ZZ) and Output Enable. Output Enable can ZBT SRAMs be used to override the synchronous control of the output 1.8 V or 2.5 V core power supply drivers and turn the RAM s output drivers off at any time. 1.8 V or 2.5 V I/O supply Write cycles are internally self-timed and initiated by the rising User-configurable Pipeline and Flow Through mode edge of the clock input. This feature eliminates complex off- ZQ mode pin for user-selectable high/low output drive chip write pulse generation required by asynchronous SRAMs IEEE 1149.1 JTAG-compatible Boundary Scan and simplifies input signal timing. LBO pin for Linear or Interleave Burst mode Pin-compatible with 2Mb, 4Mb, 8Mb, 36Mb, 72Mb and The GS8162Z18/36D-xxxV may be configured by the user to 144Mb devices operate in Pipeline or Flow Through mode. Operating as a Byte write operation (9-bit Bytes) pipelined synchronous device, in addition to the rising-edge- 3 chip enable signals for easy depth expansion triggered registers that capture input signals, the device ZZ Pin for automatic power-down incorporates a rising edge triggered output register. For read JEDEC-standard 119- and 165-Bump BGA package cycles, pipelined SRAM output data is temporarily stored by RoHS-compliant packages available the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of Functional Description clock. The GS8162Z18/36D-xxxV is an 18Mbit Synchronous Static SRAM. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL or The GS8162Z18/36D-xxxV is implemented with GSI s high other pipelined read/double late write or flow through read/ performance CMOS technology and is available in a JEDEC- single late write SRAMs, allow utilization of all available bus standard 119-bump or 165-bump BGA package. bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Parameter Synopsis -333 -250 -200 -150 Unit t 3.0 3.0 3.0 3.8 ns KQ 3.0 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 305 245 205 175 mA Curr (x36) 360 285 235 195 mA t 5.0 5.5 6.5 7.5 ns KQ Flow 5.0 5.5 6.5 7.5 ns tCycle Through Curr (x18) 235 215 205 190 mA 2-1-1-1 Curr (x36) 265 245 225 205 mA Rev: 1.03b 9/2013 1/35 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8162Z18/36D(B/D)-xxxV GS8162Z36DGB-xxxV Pad Out119-Bump BGATop View (Package B) 1 2 3 4 5 6 7 V V A A A A A A A DDQ DDQ B NC E2 A ADV A E3 NC B V C NC A A A A NC C DD V V D DQC DQPC ZQ DQPB DQB D SS SS V V E DQC DQC E1 DQB DQB E SS SS V V V V F DQC G DQB F DDQ SS SS DDQ G DQC DQC BC A BB DQB DQB G V V H DQC DQC W DQB DQB H SS SS V V V V V J NC NC J DDQ DD DD DD DDQ V V K DQD DQD CK DQA DQA K SS SS L DQD DQD BD NC BA DQA DQA L V V V V M DQD CKE DQA M DDQ SS SS DDQ V V N DQD DQD A1 DQA DQA N SS SS P DQD DQPD V A0 V DQPA DQA P SS SS V R NC A LBO FT A NC R DD T NC NC A A A NC ZZ T V V U TMS TDI TCK TDO NC U DDQ DDQ 2 7 x 17 Bump BGA14 x 22 mm Body1.27 mm Bump Pitch Rev: 1.03b 9/2013 2/35 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see