GS8170LW36/72AC-350/333/300/250 250 MHz350 MHz 209-Bump BGA 18Mb 1x1Lp CMOS I/O 1.8 V V DD Commercial Temp 1.8 V I/O Late Write SigmaRAM Industrial Temp Features Late Write mode, Pipelined Read mode JEDEC-standard SigmaRAM pinout and package 1.8 V +150/100 mV core power supply 1.8 V CMOS Interface ZQ controlled user-selectable output drive strength Dual Cycle Deselect Burst Read and Write option Fully coherent read and write pipelines Echo Clock outputs track data output drivers Byte write operation (9-bit bytes) 2 user-programmable chip enable inputs IEEE 1149.1 JTAG-compliant Serial Boundary Scan 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package Pin-compatible with future 36Mb, 72Mb, and 144Mb devices Pb-Free 209-bump BGA package available Bottom View SigmaRAM Family Overview 209-Bump, 14 mm x 22 mm BGA 1 mm Bump Pitch, 11 x 19 Bump Array GS8170LW36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, Functional Description very low voltage CMOS I/O SRAMs is designed to operate at Because SigmaRAMs are synchronous devices, address data the speeds needed to implement economical high performance inputs and read/write control inputs are captured on the rising networking systems. edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature RAMs are offered in a number of configurations including eliminates complex off-chip write pulse generation required by Late Write, Double Late Write, and Double Data Rate (DDR). asynchronous SRAMs and simplifies input signal timing. The logical differences between the protocols employed by RAMs support pipelined reads utilizing a rising-edge- these RAMs mainly involve various approaches to write triggered output register. They also utilize a Dual Cycle cueing and data transfer rates. The RAM family standard Deselect (DCD) output deselect protocol. allows a user to implement the interface protocol best suited to the task at hand. RAMs are implemented with high performance CMOS technology and are packaged in a 209-bump BGA. Parameter Synopsis Key Fast Bin Specs Symbol - 350 Cycle Time tKHKH 2.86 ns Access Time tKHQV 1.7 ns Rev: 1.04 4/2005 1/32 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8170LW36/72AC-350/333/300/250 SigmaRAM Pinouts 256K x 72 Common I/OTop View (Package C) 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A E2 A ADV A E3 A DQb DQb B DQg DQg Bc Bg NC W A Bb Bf DQb DQb C DQg DQg Bh Bd NC E1 NC Be Ba DQb DQb (144M) D DQg DQg V NC NC MCL NC NC V DQb DQb SS SS E DQg DQc V V V V V V V DQf DQb DDQ DDQ DD DD DD DDQ DDQ F DQc DQc V V V ZQ V V V DQf DQf SS SS SS SS SS SS G DQc DQc V V V EP2 V V V DQf DQf DDQ DDQ DD DD DDQ DDQ H DQc DQc V V V EP3 V V V DQf DQf SS SS SS SS SS SS J DQc DQc V V V MCL V V V DQf DQf DDQ DDQ DD DD DDQ DDQ K CQ2 CQ2 CK NC V MCL V NC NC CQ1 CQ1 SS SS L DQh DQh V V V MCH V V V DQa DQa DDQ DDQ DD DD DDQ DDQ M DQh DQh V V V MCH V V V DQa DQa SS SS SS SS SS SS N DQh DQh V V V MCH V V V DQa DQa DDQ DDQ DD DD DDQ DDQ P DQh DQh V V V MCL V V V DQa DQa SS SS SS SS SS SS R DQd DQh V V V V V V V DQa DQe DDQ DDQ DD DD DD DDQ DDQ T DQd DQd V NC NC MCL NC NC V DQe DQe SS SS U DQd DQd NC A NC A NC A NC DQe DQe (72M) (36M) V DQd DQd A A A A1 A A A DQe DQe W DQd DQd TMS TDI A A0 A TDO TCK DQe DQe 2 2002.06 11 x 19 Bump BGA14 x 22 mm Body1 mm Bump Pitch Note: Users of CMOS I/O SigmaRAMs may wish to connect NC, V and the NC, CK pins to V (i.e., V /2) to REF REF DDQ allow alternate use of future HSTL I/O SigmaRAMs. Rev: 1.04 4/2005 2/32 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see