GS8182D37BGD-400 GSI Technology

GS8182D19/37BD-435/400/375/333/300 435 MHz300 MHz 165-Bump BGA 18Mb SigmaQuad-II+ 1.8 V V DD Commercial Temp 1.8 V and 1.5 V I/O Industrial Temp Burst of 4 SRAM one element in a family of low power, low voltage HSTL I/O Features SRAMs designed to operate at the speeds needed to implement 2.0 Clock Latency economical high performance networking systems. Simultaneous Read and Write SigmaQuad Interface JEDEC-standard pinout and package Dual Double Data Rate interface Clocking and Addressing Schemes Byte Write controls sampled at data-in time Burst of 4 Read and Write The GS8182D19/37D SigmaQuad-II+ SRAMs are 1.8 V +100/100 mV core power supply synchronous devices. They employ two input register clock 1.5 V or 1.8 V HSTL Interface inputs, K and K. K and K are independent single-ended clock Pipelined read operation inputs, not differential inputs to a single differential clock input Fully coherent read and write pipelines buffer. ZQ pin for programmable output drive strength Data Valid Pin (QVLD) Each internal read and write operation in a SigmaQuad-II B4 IEEE 1149.1 JTAG-compliant Boundary Scan RAM is four times wider than the device I/O bus. An input 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package data bus de-multiplexer is used to accumulate incoming data RoHS-compliant 165-bump BGA package available before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the SigmaQuad Family Overview appropriate output drivers as needed. Therefore the address The GS8182D19/37D are built in compliance with the field of a SigmaQuad-II B4 RAM is always two address pins SigmaQuad-II+ SRAM pinout standard for Separate I/O less than the advertised index depth (e.g., the 2M x 8 has a synchronous SRAMs. They are 18,874,368-bit (18Mb) 512K addressable index). SRAMs. The GS8182D19/37D SigmaQuad SRAMs are just Parameter Synopsis -435 -400 -375 -333 -300 tKHKH 2.3 ns 2.5 ns 2.67 ns 3.3 ns 3.0 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns Rev: 1.03a 11/2011 1/27 2008, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8182D19/37BD-435/400/375/333/300 512K x 36 SigmaQuad-II+ SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 NC/SA NC/SA NC/SA NC/SA A CQ W BW2 K BW1 R CQ (288Mb) (72 Mb) (36Mb) (144Mb) B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8 C D27 Q28 D19 V SA NC SA V D16 Q7 D8 SS SS D D28 D20 Q19 V V V V V Q16 D15 D7 SS SS SS SS SS E Q29 D29 Q20 V V V V V Q15 D6 Q6 DDQ SS SS SS DDQ F Q30 Q21 D21 V V V V V D14 Q14 Q5 DDQ DD SS DD DDQ G D30 D22 Q22 V V V V V Q13 D13 D5 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J D31 Q31 D23 V V V V V D12 Q4 D4 DDQ DD SS DD DDQ K Q32 D32 Q23 V V V V V Q12 D3 Q3 DDQ DD SS DD DDQ L Q33 Q24 D24 V V V V V D11 Q11 Q2 DDQ SS SS SS DDQ M D33 Q34 D25 V V V V V D10 Q1 D2 SS SS SS SS SS N D34 D26 Q25 V SA SA SA V Q10 D9 D1 SS SS P Q35 D35 Q26 SA SA QVLD SA SA Q9 D0 Q0 R TDO TCK SA SA SA NC SA SA SA TMS TDI 2 11 x 15 Bump BGA13 x 15 mm Body1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8 BW1 controls writes to D9:D17 BW2 controls writes to D18:D26 BW3 controls writes to D27:D35 2. NC = Not connected Rev: 1.03a 11/2011 2/27 2008, GSI Technology Specifications cited are subject to change without notice. For latest documentation see