GS8182T08/09/18/36BD-400/375/333/300/250/200/167 400 MHz167 MHz 165-Bump BGA 18Mb SigmaDDR-II 1.8 V V Commercial Temp DD Burst of 2 SRAM Industrial Temp 1.8 V and 1.5 V I/O inputs, not differential inputs to a single differential clock input Features buffer. The device also allows the user to manipulate the Simultaneous Read and Write SigmaDDR-II Interface output register clock inputs quasi independently with the C and Common I/O bus C clock inputs. C and C are also independent single-ended JEDEC-standard pinout and package clock inputs, not differential inputs. If the C clocks are tied Double Data Rate interface high, the K clocks are routed internally to fire the output Byte Write (x36 and x18) and Nybble Write (x8) function registers instead. Burst of 2 Read and Write 1.8 V +100/100 mV core power supply Each internal read and write operation in a SigmaDDR-II B2 1.5 V or 1.8 V HSTL Interface RAM is two times wider than the device I/O bus. An input data Pipelined read operation with self-timed Late Write bus de-multiplexer is used to accumulate incoming data before Fully coherent read and write pipelines it is simultaneously written to the memory array. An output ZQ pin for programmable output drive strength data multiplexer is used to capture the data produced from a IEEE 1149.1 JTAG-compliant Boundary Scan single memory array read and then route it to the appropriate Pin-compatible with present 9Mb, 36Mb, and 72Mb and output drivers as needed. future 144Mb devices 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package When a new address is loaded into a x18 or x36 version of the RoHS-compliant 165-bump BGA package available part, A0 is used to initialize the pointers that control the data multiplexer / de-multiplexer so the RAM can performcritical SigmaDDR-II Family Overview word firs operations. From an external address point of view, The GS8182T08/09/18/36BD are built in compliance with the regardless of the starting point, the data transfers always follow SigmaDDR-II SRAM pinout standard for Common I/O the same sequence 0, 1 or 1, 0 (where the digits shown synchronous SRAMs. They are 18,874,368-bit (18Mb) represent A0). SRAMs. The GS8182T08/09/18/36BD SigmaDDR-II SRAMs are just one element in a family of low power, low voltage Unlike the x18 and x36 versions, the input and output data HSTL I/O SRAMs designed to operate at the speeds needed to multiplexers of the x8 and x9 versions are not preset by implement economical high performance networking systems. address inputs and therefore do not allowcritical word firs operations. The address fields of the x8 and x9 SigmaDDR-II Clocking and Addressing Schemes B2 RAMs are one address pin less than the advertised index depth (e.g., the 2M x 8 has a 1M addressable index, and A0 is The GS8182T08/09/18/36BD SigmaDDR-II SRAMs are not an accessible address pin). synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock Parameter Synopsis -400 -375 -333 -300 -250 -200 -167 tKHKH 2.5 ns 2.67 ns 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.5 ns Rev: 1.04c 11/2011 1/36 2007, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8182T08/09/18/36BD-400/375/333/300/250/200/167 512K x 36 SigmaDDR-II SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 NC/SA NC/SA NC/SA A CQ R/W BW2 K BW1 LD SA CQ (144Mb) (36Mb) (72Mb) NC/SA B NC DQ27 DQ18 SA BW3 K BW0 SA NC DQ8 (288Mb) C NC NC DQ28 V SA SA0 SA V NC DQ17 DQ7 SS SS D NC DQ29 DQ19 V V V V V NC NC DQ16 SS SS SS SS SS E NC NC DQ20 V V V V V NC DQ15 DQ6 DDQ SS SS SS DDQ F NC DQ30 DQ21 V V V V V NC NC DQ5 DDQ DD SS DD DDQ G NC DQ31 DQ22 V V V V V NC NC DQ14 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC DQ32 V V V V V NC DQ13 DQ4 DDQ DD SS DD DDQ K NC NC DQ23 V V V V V NC DQ12 DQ3 DDQ DD SS DD DDQ L NC DQ33 DQ24 V V V V V NC NC DQ2 DDQ SS SS SS DDQ M NC NC DQ34 V V V V V NC DQ11 DQ1 SS SS SS SS SS N NC DQ35 DQ25 V SA SA SA V NC NC DQ10 SS SS P NC NC DQ26 SA SA C SA SA NC DQ9 DQ0 R TDO TCK SA SA SA C SA SA SA TMS TDI 2 11 x 15 Bump BGA13 x 15 mm Body1 mm Bump Pitch Notes: 1. BW0 controls writes to DQ0:DQ8 BW1 controls writes to DQ9:DQ17 BW2 controls writes to DQ18:DQ26 BW3 controls writes to DQ27:DQ35. Rev: 1.04c 11/2011 2/36 2007, GSI Technology Specifications cited are subject to change without notice. For latest documentation see