GS8256418/36(GB/GD)-xxxV 119- & 165-Bump BGA 333 MHz200 MHz 16M x 18, 8M x 36 Commercial Temp 1.8 V or 2.5 V V DD 288Mb DCD Sync Burst SRAMs Industrial Temp 1.8 V or 2.5 V I/O either linear or interleave order with the Linear Burst Order (LBO) Features input. The Burst function need not be used. New addresses can be FT pin for user-configurable flow through or pipeline operation Single/Dual Cycle Deselect selectable loaded on every cycle with no degradation of chip performance. IEEE 1149.1 JTAG-compatible Boundary Scan Flow Through/Pipeline Reads ZQ mode pin for user-selectable high/low output drive The function of the Data Output register can be controlled by the 1.8 V +10%/10% core power supply user via the FT mode . Holding the FT mode pin low places the 2.5 V +10%/10% core power supply RAM in Flow Through mode, causing output data to bypass the 1.8 V or 2.5 V I/O supply Data Output Register. Holding FT high places the RAM in LBO pin for Linear or Interleaved Burst mode Pipeline mode, activating the rising-edge-triggered Data Output Internal input resistors on mode pins allow floating mode pins Register. Byte Write (BW) and/or Global Write (GW) operation DCD Pipelined Reads Internal self-timed write cycle The GS8256418/36-xxxV is a DCD (Dual Cycle Deselect) ZZ pin for automatic power-down pipelined synchronous SRAM. DCD SRAMs pipeline disable RoHS-compliant 119-bump and 165-bump BGA packages commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin Functional Description turning off their outputs just after the second rising edge of clock. Applications The GS8256418/36-xxxV is a 301,989,888-bit high performance Byte Write and Global Write synchronous SRAM with a 2-bit burst address counter. Although Byte write operation is performed by using Byte Write enable of a type originally developed for Level 2 Cache applications (BW) input combined with one or more individual byte write supporting high performance CPUs, the device now finds signals (Bx). In addition, Global Write (GW) is available for application in synchronous SRAM applications, ranging from writing all bytes at one time, regardless of the Byte Write control DSP main store to networking chip set support. inputs. Controls FLXDrive Addresses, data I/Os, chip enable (E1), address burst control The ZQ pin allows selection between high drive strength (ZQ low) inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, for multi-drop bus applications and normal drive strength (ZQ GW) are synchronous and are controlled by a positive-edge- floating or high) point-to-point applications. See the Output Driver triggered clock input (CK). Output enable (G) and power down Characteristics chart for details. control (ZZ) are asynchronous inputs. Burst cycles can be initiated Core and Interface Voltages with either ADSP or ADSC inputs. In Burst mode, subsequent The GS8256418/36-xxxV operates on a 1.8 V or 2.5 V power burst addresses are generated internally and are controlled by supply. All input are 31.8 V or 2.5 V compatible. Separate output ADV. The burst address counter may be configured to count in Parameter Synopsis -333 -250 -200 Unit t 2.5 2.5 3.0 ns KQ 3.0 4.0 5.0 ns Pipeline tCycle 3-1-1-1 Curr (x18) 630 520 450 mA Curr (x36) 690 570 490 mA t 4.5 5.5 6.5 ns KQ 4.5 5.5 6.5 ns Flow Through tCycle 2-1-1-1 Curr (x18) 490 430 400 mA Curr (x36) 530 470 440 mA Rev: 1.03 5/2017 1/32 2015, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8256418/36(GB/GD)-xxxV 119-Bump BGAx36 Common I/OTop View 1 2 3 4 5 6 7 V V A A A ADSP A A A DDQ DDQ B A A A ADSC A A NC B V C A A A A A NC C DD V V D DQC DQPC ZQ DQPB DQB D SS SS V V E DQC DQC E1 DQB DQB E SS SS F V DQC V G V DQB V F DDQ SS SS DDQ G DQC2 DQC BC ADV BB DQB DQB G V V H DQC DQC GW DQB DQB H SS SS V V V V V J NC NC J DDQ DD DD DD DDQ V V K DQD DQD CK DQA DQA K SS SS L DQD DQD BD NU BA DQA DQA L V V V V M DQD BW DQA M DDQ SS SS DDQ V V N DQD DQD A1 DQA DQA N SS SS V P DQD DQPD A0 V DQPA DQA P SS SS V R NC A LBO FT A NC R DD T NC A A A A A ZZ T V V U TMS TDI TCK TDO NC U DDQ DDQ 2 7 x 17 Bump BGA14 x 22 mm Body1.27 mm Bump Pitch Rev: 1.03 5/2017 2/32 2015, GSI Technology Specifications cited are subject to change without notice. For latest documentation see