GS82564Z18/36(GB/GD)-xxxV 119- & 165-Bump BGA 333 MHz200 MHz 288Mb Pipelined and Flow Through Commercial Temp 1.8 V or 2.5 V V DD Synchronous NBT SRAM Industrial Temp 1.8 V or 2.5 V I/O Features Because it is a synchronous device, address, data inputs, and NBT (No Bus Turn Around) functionality allows zero wait read/write control inputs are captured on the rising edge of the Read-Write-Read bus utilization fully pin-compatible with input clock. Burst order control (LBO) must be tied to a power both pipelined and flow through NtRAM, NoBL and rail for proper operation. Asynchronous inputs include the ZBT SRAMs Sleep mode enable (ZZ) and Output Enable. Output Enable can 1.8 V or 2.5 V +10%/10% core power supply be used to override the synchronous control of the output 1.8 V or 2.5 V I/O supply drivers and turn the RAM s output drivers off at any time. User-configurable Pipeline and Flow Through mode Write cycles are internally self-timed and initiated by the rising ZQ mode pin for user-selectable high/low output drive edge of the clock input. This feature eliminates complex off- IEEE 1149.1 JTAG-compatible Boundary Scan chip write pulse generation required by asynchronous SRAMs LBO pin for Linear or Interleave Burst mode and simplifies input signal timing. Pin-compatible with 4Mb, 9Mb, 18Mb, 36Mb, and 72Mb devices The GS82564Z18/36-xxxV may be configured by the user to Byte write operation (9-bit Bytes) operate in Pipeline or Flow Through mode. Operating as a 3 chip enable signals for easy depth expansion pipelined synchronous device, in addition to the rising-edge- ZZ Pin for automatic power-down triggered registers that capture input signals, the device RoHS-compliant 119- and 165-bump BGA packages incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by Functional Description the edge-triggered output register during the access cycle and The GS82564Z18/36-xxxV is a 288Mbit Synchronous Static then released to the output drivers at the next rising edge of SRAM. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL or clock. other pipelined read/double late write or flow through read/ The GS82564Z18/36-xxxV is implemented with GSI s high single late write SRAMs, allow utilization of all available bus performance CMOS technology and is available in a JEDEC- bandwidth by eliminating the need to insert deselect cycles standard 119-bump or 165-bump BGA package. when the device is switched from read to write cycles. Parameter Synopsis -333 -250 -200 Unit t 2.5 2.5 3.0 ns KQ 3.0 4.0 5.0 ns Pipeline tCycle 3-1-1-1 Curr (x18) 630 520 450 mA Curr (x36) 690 570 490 mA t 4.5 5.5 6.5 ns KQ 4.5 5.5 6.5 ns Flow Through tCycle 2-1-1-1 Curr (x18) 490 430 400 mA Curr (x36) 530 470 440 mA Rev: 1.02b 11/2018 1/32 2015, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS82564Z18/36(GB/GD)-xxxV GS82564Z36GB Pad Out119-Bump BGATop View 1 2 3 4 5 6 7 A V A A A A A V A DDQ DDQ B NC E2 A ADV A E3 NC B C NC A A V A A NC C DD D DQC D Q PC V ZQ V D Q PB DQB D SS SS E DQC DQC V E1 V DQB DQB E SS SS F V DQC V G V DQB V F DDQ SS SS DDQ G DQC DQC BC A BB DQB DQB G H DQC DQC V W V DQB DQB H SS SS J V V NC V NC V V J DDQ DD DD DD DDQ K DQD DQD V CK V DQA DQA K SS SS L DQD DQD BD NC BA DQA DQA L M V DQD V CKE V DQA V M DDQ SS SS DDQ N DQD DQD V A1 V DQA DQA N SS SS P DQD D Q PD V A0 V D Q PA DQA P SS SS R A A LBO V FT A A R DD T NC A A A A A ZZ T U V TMS TDI TCK TDO NC V U DDQ DDQ 2 7 x 17 Bump BGA14 x 22 mm Body1.27 mm Bump Pitch Rev: 1.02b 11/2018 2/32 2015, GSI Technology Specifications cited are subject to change without notice. For latest documentation see