GS82582TT20/38GE-550/500/450/400 550 MHz400 MHz 165-Bump BGA TM 288Mb SigmaDDR-II+ 1.8 V V Commercial Temp DD Industrial Temp Burst of 2 SRAM 1.8 V or 1.5 V I/O are just one element in a family of low power, low voltage Features HSTL I/O SRAMs designed to operate at the speeds needed to 2.5 Clock Latency implement economical high performance networking systems. TM Simultaneous Read and Write SigmaDDR Interface JEDEC-standard pinout and package Clocking and Addressing Schemes Double Data Rate interface The GS82582TT20/38GE SigmaDDR-II+ SRAMs are Byte Write controls sampled at data-in time synchronous devices. They employ two input register clock Burst of 2 Read and Write inputs, K and K. K and K are independent single-ended clock Dual-Range On-Die Termination (ODT) on Data (D), Byte inputs, not differential inputs to a single differential clock input Write (BW), and Clock (K, K) inputs buffer. 1.8 V +100/100 mV core power supply 1.5 V or 1.8 V HSTL Interface Each internal read and write operation in a SigmaDDR-II+ B2 Pipelined read operation RAM is two times wider than the device I/O bus. An input data Fully coherent read and write pipelines bus de-multiplexer is used to accumulate incoming data before ZQ pin for programmable output drive strength it is simultaneously written to the memory array. An output Data Valid Pin (QVLD) Support data multiplexer is used to capture the data produced from a IEEE 1149.1 JTAG-compliant Boundary Scan single memory array read and then route it to the appropriate RoHS-compliant 165-bump BGA package output drivers as needed. Therefore, the address field of a SigmaDDR-II+ B2 RAM is always one address pin less than SigmaDDR-II Family Overview the advertised index depth (e.g., the 16M x 18 has an 8M The GS82582TT20/38GE are built in compliance with the addressable index). SigmaDDR-II+ SRAM pinout standard for Common I/O synchronous SRAMs. They are 301,989,888-bit (288Mb) SRAMs. The GS82582TT20/38GE SigmaDDR-II+ SRAMs Parameter Synopsis -550 -500 -450 -400 tKHKH 1.81 ns 2.0 ns 2.2 ns 2.5 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns Rev: 1.03b 11/2017 1/24 2012, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS82582TT20/38GE-550/500/450/400 8M x 36 SigmaDDR-II+ SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 A CQ SA SA R/W BW2 K BW1 LD SA SA CQ B NC DQ27 DQ18 SA BW3 K BW0 SA SA NC DQ8 C NC NC DQ28 V SA NC SA V NC DQ17 DQ7 SS SS D NC DQ29 DQ19 V V V V V NC NC DQ16 SS SS SS SS SS E NC NC DQ20 V V V V V NC DQ15 DQ6 DDQ SS SS SS DDQ F NC DQ30 DQ21 V V V V V NC NC DQ5 DDQ DD SS DD DDQ G NC DQ31 DQ22 V V V V V NC NC DQ14 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC DQ32 V V V V V NC DQ13 DQ4 DDQ DD SS DD DDQ K NC NC DQ23 V V V V V NC DQ12 DQ3 DDQ DD SS DD DDQ L NC DQ33 DQ24 V V V V V NC NC DQ2 DDQ SS SS SS DDQ M NC NC DQ34 V V V V V NC DQ11 DQ1 SS SS SS SS SS N NC DQ35 DQ25 V SA SA SA V NC NC DQ10 SS SS P NC NC DQ26 SA SA QVLD SA SA NC DQ9 DQ0 R TDO TCK SA SA SA ODT SA SA SA TMS TDI 2 11 x 15 Bump BGA15 x 17 mm Body1 mm Bump Pitch Note: BW0 controls writes to DQ0:DQ8 BW1 controls writes to DQ9:DQ17 BW2 controls writes to DQ18:DQ26 BW3 controls writes to DQ27:DQ35. Rev: 1.03b 11/2017 2/24 2012, GSI Technology Specifications cited are subject to change without notice. For latest documentation see