GS82583EQ18/36GK-500/450/400 Up to 500 MHz 260-Pin BGA 288Mb SigmaQuad-IIIe 1.3V V Commercial Temp DD Burst of 2 SRAM Industrial Temp 1.2V, 1.3V, or 1.5V V DDQ Features Clocking and Addressing Schemes 8Mb x 36 and 16Mb x 18 organizations available The GS82583EQ18/36GK SigmaQuad-IIIe SRAMs are synchronous devices. They employ three pairs of positive and 500 MHz maximum operating frequency negative input clocks one pair of master clocks, CK and CK, 1.0 BT/s peak transaction rate (in billions per second) and two pairs of write data clocks, KD 1:0 and KD 1:0 . All 72 Gb/s peak data bandwidth (in x36 devices) six input clocks are single-ended that is, each is received by a Separate I/O DDR Data Buses dedicated input buffer. Non-multiplexed DDR Address Bus Two operations - Read and Write - per clock cycle CK and CK are used to latch address and control inputs, and to Burst of 2 Read and Write operations control all output timing. KD 1:0 and KD 1:0 are used solely 3 cycle Read Latency to latch data inputs. 1.3V nominal core voltage 1.2V, 1.3V, or 1.5V HSTL I/O interface Each internal read and write operation in a SigmaQuad-IIIe B2 Configurable ODT (on-die termination) SRAM is two times wider than the device I/O bus. An input ZQ pin for programmable driver impedance data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An ZT pin for programmable ODT impedance output data multiplexer is used to capture the data produced IEEE 1149.1 JTAG-compliant Boundary Scan from a single memory array read and then route it to the 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS- appropriate output drivers as needed. Therefore, the address compliant BGA package field of a SigmaQuad-IIIe B2 SRAM is always one address pin less than the advertised index depth (e.g. the 16M x 18 has 8M SigmaQuad-IIIe Family Overview addressable index). SigmaQuad-IIIe SRAMs are the Separate I/O half of the SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance SRAMs. Although very similar to GSI s second generation of networking SRAMs (the SigmaQuad-II/SigmaDDR-II family), these third generation devices offer several new features that help enable significantly higher performance. Parameter Synopsis V Speed Grade Max Operating Frequency Read Latency DD -500 500 MHz 3 cycles 1.25V to 1.35V -450 450 MHz 3 cycles 1.25V to 1.35V -400 400 MHz 3 cycles 1.25V to 1.35V Rev: 1.07 12/2017 1/26 2014, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS82583EQ18/36GK-500/450/400 16M x 18 Pinout (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 NC MCH V V V V MCL V V V V ZQ PZT1 A DD DDQ DD DDQ DDQ DD DDQ DD (RSVD) (CFG) MCL NC MCH V NU V NU V V B MVQ PZT0 D0 Q0 SS O SS I SS SS (B4M) (RSVD) (SIOM) V V V V V V NU V NU Q17 D17 SA SA C DDQ DDQ SS DD SS DDQ I DDQ O V NU V NU V V V V D SA SA SA D1 Q1 SS O SS I DDQ DDQ SS SS Q16 V D16 V V SA V SA V V NU V NU E DDQ DD SS SS SS DD I DDQ O V NU V NU V V V V V SA SA D2 Q2 F SS O SS I DD DDQ DD SS SS NU NU V V NU NU G Q15 D15 SA MZT1 SA D3 Q3 O I SS SS I O V V V V V NU V NU Q14 D14 SA W SA H DDQ DDQ DDQ DDQ DDQ I DDQ O V NU V NU V V V V V J SA SA D4 Q4 SS O SS I SS SS SS SS SS CQ1 V V V KD1 V CK V KD0 V V V CQ0 K DDQ REF DD DD DD DD REF DDQ V V V V V V CQ1 QVLD1 KD1 CK KD0 QVLD0 CQ0 L SS ss DDQ DDQ SS SS V V V V V NU V NU V M Q13 D13 SA SA SS SS SS SS SS I SS O SS NU V NU V V V V V DLL R MCH D5 Q5 N O DDQ I DDQ DDQ DDQ DDQ DDQ NU NU V V NU NU P Q12 D12 SA MZT0 SA D6 Q6 O I SS SS I O V Q11 V D11 MCH V V V RST NU V NU V R SS SS DD DDQ DD I SS O SS NU V NU V V V V V V SA SA D7 Q7 T O DDQ I DD SS SS SS DD DDQ NC NC NC V V V V NU V NU V U Q10 D10 SS SS DDQ DDQ I SS O SS (576 Mb) (RSVD) (1152 Mb) SA SA NU V NU V V V V V V D8 Q8 V O DDQ I DDQ SS DD SS DDQ DDQ (x18) (B2) NC V V NU V NU V W Q9 D9 TCK MCL MCL TMS SS SS I SS O SS (RSVD) NC V V V V TDO ZT MCL TDI V V V V Y DD DDQ DD DDQ DDQ DD DDQ DD (RSVD) Notes: 1. Pins 6W, 7A, 8W, and 8Y must be tied Low in this device. 2. Pins 5R and 9N must be tied High in this device. 3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration. 4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration. 5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied Low in this device to select Burst-of-2 configuration. 6. Pin 6V is defined as address pin SA for x18 devices. It is used in this device. 7. Pin 8V is defined as address pin SA for B2 devices. It is used in this device. 8. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device. 9. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device. Rev: 1.07 12/2017 2/26 2014, GSI Technology Specifications cited are subject to change without notice. For latest documentation see