GS82583ET18/36GK-675/625/550/500 Up to 675 MHz 260-Pin BGA 288Mb SigmaDDR-IIIe 1.3V V Commercial Temp DD Burst of 2 SRAM Industrial Temp 1.2V, 1.3V, or 1.5V V DDQ Features Clocking and Addressing Schemes 8Mb x 36 and 16Mb x 18 organizations available The GS82583ET18/36GK SigmaDDR-IIIe SRAMs are synchronous devices. They employ three pairs of positive and 675 MHz maximum operating frequency negative input clocks one pair of master clocks, CK and CK, 675 MT/s peak transaction rate (in millions per second) and two pairs of write data clocks, KD 1:0 and KD 1:0 . All 48 Gb/s peak data bandwidth (in x36 devices) six input clocks are single-ended that is, each is received by a Common I/O DDR Data Bus dedicated input buffer. Non-multiplexed SDR Address Bus One operation - Read or Write - per clock cycle CK and CK are used to latch address and control inputs, and to Burst of 2 Read and Write operations control all output timing. KD 1:0 and KD 1:0 are used solely 3 cycle Read Latency to latch data inputs. 1.3V nominal core voltage 1.2V, 1.3V, or 1.5V HSTL I/O interface Each internal read and write operation in a SigmaDDR-IIIe B2 Configurable ODT (on-die termination) SRAM is two times wider than the device I/O bus. An input ZQ pin for programmable driver impedance data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An ZT pin for programmable ODT impedance output data multiplexer is used to capture the data produced IEEE 1149.1 JTAG-compliant Boundary Scan from a single memory array read and then route it to the 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS- appropriate output drivers as needed. Therefore, the address compliant BGA package field of a SigmaDDR-IIIe B2 SRAM is always one address pin less than the advertised index depth (e.g. the 16M x 18 has 8M SigmaDDR-IIIe Family Overview addressable index). SigmaDDR-IIIe SRAMs are the Common I/O half of the SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance SRAMs. Although very similar to GSI s second generation of networking SRAMs (the SigmaQuad-II/SigmaDDR-II family), these third generation devices offer several new features that help enable significantly higher performance. Parameter Synopsis V Speed Grade Max Operating Frequency Read Latency DD -675 675 MHz 3 cycles 1.25V to 1.35V -625 625 MHz 3 cycles 1.25V to 1.35V -550 550 MHz 3 cycles 1.25V to 1.35V -500 500 MHz 3 cycles 1.25V to 1.35V Rev: 1.07 12/2017 1/29 2014, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS82583ET18/36GK-675/625/550/500 16M x 18 Pinout (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 NC MCH MCL V V V V ZQ PZT1 V V V V A DD DDQ DD DDQ DDQ DD DDQ DD (RSVD) (CFG) NC MCL V NU V NU NU V V MVQ MCL PZT0 DQ0 B SS IO SS I I SS SS (RSVD) (SIOM) V NU V V V V V NU V NU C DQ17 SA SA DDQ I DDQ SS DD SS DDQ I DDQ IO V NU V NU V V NU V V SA SA SA DQ1 D SS IO SS I DDQ DDQ I SS SS V NU V V V V V NU V NU E DQ16 SA SA SS DDQ I DD SS SS DD I DDQ IO V NU V NU SA V V V SA NU V DQ2 V F SS IO SS I DD DDQ DD I SS SS NU NU NU V V NU NU NU DQ15 SA MZT1 SA DQ3 G IO I I SS SS I I IO V NU V V V V NU V NU H DQ14 SA R/W SA DDQ I DDQ DDQ DDQ DDQ I DDQ IO V NU V NU V V V NU V V SA SA DQ4 J SS IO SS I SS SS SS I SS SS V V V V V V V V K CQ1 KD1 CK KD0 CQ0 DDQ REF DD DD DD DD REF DDQ CQ1 V QVLD1 V KD1 V CK V KD0 V QVLD0 V CQ0 L SS SS DDQ DDQ SS SS V V NU V V V NU V NU V DQ13 SA SA M SS SS I SS SS SS I SS IO SS NU V NU V V V V NU V N DLL LD MCH DQ5 IO DDQ I DDQ DDQ DDQ DDQ I DDQ NU NU NU V V NU NU NU DQ12 SA MZT0 SA DQ6 P IO I I SS SS I I IO V V NU V V V NU V NU V R DQ11 MCH RST SS SS I DD DDQ DD I SS IO SS NU V NU V V SA V SA V V NU V DQ7 T IO DDQ I DD SS SS SS DD I DDQ NC NC NC V V NU V V NU V NU V DQ10 U SS SS I DDQ DDQ I SS IO SS (576 Mb) (RSVD) (1152 Mb) SA SA NU V NU V V V V V NU V V DQ8 IO DDQ I DDQ SS DD SS DDQ I DDQ (x18) (B2) NC V V NU NU V NU V DQ9 TCK MCL MCL TMS W SS SS I I SS IO SS (RSVD) NC V V V V V V V V Y TDO ZT MCL TDI DD DDQ DD DDQ DDQ DD DDQ DD (RSVD) Notes: 1. Pins 6B, 6W, 7A, 8W, and 8Y must be tied Low in this device. 2. Pins 5R and 9N must be tied High in this device. 3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration. 4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration. 5. Pin 6V is defined as address pin SA for x18 devices. It is used in this device. 6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device. 7. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device. 8. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device. Rev: 1.07 12/2017 2/29 2014, GSI Technology Specifications cited are subject to change without notice. For latest documentation see