GS832018/32/36AGT-xxxV 333 MHz150 MHz 100-Pin TQFP 2M x 18, 1M x 32, 1M x 36 1.8 V or 2.5 V V Commercial Temp DD 36Mb Sync Burst SRAMs Industrial Temp 1.8 V or 2.5 V I/O cycles can be initiated with either ADSP or ADSC inputs. In Features Burst mode, subsequent burst addresses are generated FT pin for user-configurable flow through or pipeline internally and are controlled by ADV. The burst address operation counter may be configured to count in either linear or Single Cycle Deselect (SCD) operation interleave order with the Linear Burst Order (LBO) input. The 1.8 V or 2.5 V core power supply Burst function need not be used. New addresses can be loaded 1.8 V or 2.5 V I/O supply on every cycle with no degradation of chip performance. LBO pin for Linear or Interleaved Burst mode Internal input resistors on mode pins allow floating mode pins Flow Through/Pipeline Reads Default to Interleaved Pipeline mode The function of the Data Output register can be controlled by Byte Write (BW) and/or Global Write (GW) operation the user via the FT mode pin (Pin 14). Holding the FT mode Internal self-timed write cycle pin low places the RAM in Flow Through mode, causing Automatic power-down for portable applications output data to bypass the Data Output Register. Holding FT RoHS-compliant 100-lead TQFP package available high places the RAM in Pipeline mode, activating the rising- edge-triggered Data Output Register. Functional Description Byte Write and Global Write Byte write operation is performed by using Byte Write enable Applications (BW) input combined with one or more individual byte write The GS832018/32/36AGT-xxxV is a 37,748,736-bit high signals (Bx). In addition, Global Write (GW) is available for performance synchronous SRAM with a 2-bit burst address writing all bytes at one time, regardless of the Byte Write counter. Although of a type originally developed for Level 2 control inputs. Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM Sleep Mode applications, ranging from DSP main store to networking chip Low power (Sleep mode) is attained through the assertion set support. (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst Core and Interface Voltages control inputs (ADSP, ADSC, ADV), and write control inputs The GS832018/32/36AGT-xxxV operates on a 1.8 V power (Bx, BW, GW) are synchronous and are controlled by a supply. All input are 1.8 V compatible. Separate output power positive-edge-triggered clock input (CK). Output enable (G) (V ) pins are used to decouple output noise from the DDQ and power down control (ZZ) are asynchronous inputs. Burst internal circuits and are 1.8 V compatible. Parameter Synopsis -333 -250 -200 -150 Unit t 2.5 2.5 3.0 3.8 ns KQ 3.3 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 365 290 250 215 mA Curr (x32/x36) 425 345 290 240 mA t 4.5 5.5 6.5 7.5 ns KQ Flow 4.5 5.5 6.5 7.5 ns tCycle Through Curr (x18) 270 245 210 200 mA 2-1-1-1 Curr (x32/x36) 315 280 250 230 mA Rev: 1.03 8/2013 1/22 2011, GSI TechnologyGS832018/32/36AGT-xxxV GS832018AGT-xxxV 100-Pin TQFP Pinout 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 2M x 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 67 FT SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either V or V . These pins can also be left floating. DD SS Rev: 1.03 8/2013 2/22 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see