GS8320Z18AGT-200I GSI Technology

GS8320Z18/36AGT-400/375/333/250/200/150 400 MHz150 MHz 100-Pin TQFP 36Mb Pipelined and Flow Through 2.5 V or 3.3 V V Commercial Temp DD Synchronous NBT SRAMs Industrial Temp 2.5 V or 3.3 V I/O Because it is a synchronous device, address, data inputs, and Features read/ write control inputs are captured on the rising edge of the NBT (No Bus Turn Around) functionality allows zero wait input clock. Burst order control (LBO) must be tied to a power read-write-read bus utilization Fully pin-compatible with rail for proper operation. Asynchronous inputs include the both pipelined and flow through NtRAM, NoBL and Sleep mode enable (ZZ) and Output Enable. Output Enable can ZBT SRAMs be used to override the synchronous control of the output 2.5 V or 3.3 V +10%/10% core power supply drivers and turn the RAM s output drivers off at any time. 2.5 V or 3.3 V I/O supply Write cycles are internally self-timed and initiated by the rising User-configurable Pipeline and Flow Through mode edge of the clock input. This feature eliminates complex off- LBO pin for Linear or Interleave Burst mode chip write pulse generation required by asynchronous SRAMs Pin compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices and simplifies input signal timing. Byte write operation (9-bit Bytes) 3 chip enable signals for easy depth expansion The GS8320Z18/36AGT may be configured by the user to ZZ Pin for automatic power-down operate in Pipeline or Flow Through mode. Operating as a RoHS-compliant 100-lead TQFP package available pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the Functional Description device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored The GS8320Z18/36AGT is a 36Mbit Synchronous Static by the edge triggered output register during the access cycle SRAM. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL or and then released to the output drivers at the next rising edge of other pipelined read/double late write or flow through read/ clock. single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles The GS8320Z18/36AGT is implemented with GSI s high when the device is switched from read to write cycles. performance CMOS technology and is available in a JEDEC- standard 100-pin TQFP package. Parameter Synopsis -400 -375 -333 -250 -200 -150 Unit t 2.5 2.5 2.5 2.5 3.0 3.8 ns KQ 2.5 2.66 3.3 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 395 390 355 280 240 205 mA Curr (x36) 475 455 415 335 280 230 mA t 4.0 4.2 4.5 5.5 6.5 7.5 ns KQ Flow 4.0 4.2 4.5 5.5 6.5 7.5 ns tCycle Through Curr (x18) 290 275 260 235 200 190 mA 2-1-1-1 Curr (x36) 335 320 305 270 240 220 mA Rev: 1.03 8/2013 1/23 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8320Z18/36AGT-400/375/333/250/200/150 GS8320Z18AGT Pinout 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 2M x 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 FT 67 SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.03 8/2013 2/23 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see