GS832118/32/36AD-400/375/333/250/200/150 400 MHz150 MHz 165-Bump BGA 2M x 18, 1M x 32, 1M x 36 2.5 V or 3.3 V V Commercial Temp DD 36Mb Sync Burst SRAMs Industrial Temp 2.5 V or 3.3 V I/O Linear Burst Order (LBO) input. The Burst function need not Features be used. New addresses can be loaded on every cycle with no FT pin for user-configurable flow through or pipeline degradation of chip performance. operation Single Cycle Deselect (SCD) operation Flow Through/Pipeline Reads IEEE 1149.1 JTAG-compatible Boundary Scan The function of the Data Output register can be controlled by 2.5 V or 3.3 V +10%/10% core power supply the user via the FT mode pin (Pin 14). Holding the FT mode 2.5 V or 3.3 V I/O supply pin low places the RAM in Flow Through mode, causing LBO pin for Linear or Interleaved Burst mode output data to bypass the Data Output Register. Holding FT Internal input resistors on mode pins allow floating mode pins high places the RAM in Pipeline mode, activating the rising- Byte Write (BW) and/or Global Write (GW) operation edge-triggered Data Output Register. Internal self-timed write cycle SCD Pipelined Reads Automatic power-down for portable applications The GS832118/32/36AD is a SCD (Single Cycle Deselect) JEDEC-standard 165-bump BGA package pipelined synchronous SRAM. DCD (Dual Cycle Deselect) RoHS-compliant 165-bump BGA package available versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs Functional Description begin turning off their outputs immediately after the deselect Applications command has been captured in the input registers. The GS832118/32/36AD is a 37,748,736-bit high performance Byte Write and Global Write synchronous SRAM with a 2-bit burst address counter. Byte write operation is performed by using Byte Write enable Although of a type originally developed for Level 2 Cache (BW) input combined with one or more individual byte write applications supporting high performance CPUs, the device signals (Bx). In addition, Global Write (GW) is available for now finds application in synchronous SRAM applications, writing all bytes at one time, regardless of the Byte Write ranging from DSP main store to networking chip set support. control inputs. Controls Sleep Mode Addresses, data I/Os, chip enable (E1), address burst control Low power (Sleep mode) is attained through the assertion inputs (ADSP, ADSC, ADV) and write control inputs (Bx, (High) of the ZZ signal, or by stopping the clock (CK). BW, GW) are synchronous and are controlled by a positive- Memory data is retained during Sleep mode. edge-triggered clock input (CK). Output enable (G) and power Core and Interface Voltages down control (ZZ) are asynchronous inputs. Burst cycles can The GS832118/32/36AD operates on a 3.3 V or 2.5 V power be initiated with either ADSP or ADSC inputs. In Burst mode, supply. All input are 3.3 V and 2.5 V compatible. Separate subsequent burst addresses are generated internally and are output power (V ) pins are used to decouple output noise controlled by ADV. The burst address counter may be DDQ configured to count in either linear or interleave order with the from the internal circuits and are 3.3 V and 2.5 V compatible. Parameter Synopsis -400 -375 -333 -250 -200 -150 Unit t 2.5 2.5 2.5 2.5 3.0 3.8 ns KQ 2.5 2.66 3.3 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 395 390 355 280 240 205 mA Curr (x32/x36) 475 455 415 335 280 230 mA t 4.0 4.2 4.5 5.5 6.5 7.5 ns KQ Flow 4.0 4.2 4.5 5.5 6.5 7.5 ns tCycle Through Curr (x18) 290 275 260 235 200 190 mA 2-1-1-1 Curr (x32/x36) 335 320 305 270 240 220 mA Rev: 1.03 8/2013 1/32 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS832118/32/36AD-400/375/333/250/200/150 165 Bump BGAx18 Common I/OTop View (Package D) 1 2 3 4 5 6 7 8 9 10 11 A NC A E1 BB NC E3 BW ADSC ADV A A A B NC A E2 NC BA CK GW G ADSP A NC B C NC NC V V V V V V V NC DQPA C DDQ SS SS SS SS SS DDQ D NC DQB V V V V V V V NC DQA D DDQ DD SS SS SS DD DDQ E NC DQB V V V V V V V NC DQA E DDQ DD SS SS SS DD DDQ F NC DQB V V V V V V V NC DQA F DDQ DD SS SS SS DD DDQ G NC DQB V V V V V V V NC DQA G DDQ DD SS SS SS DD DDQ H FT MCL NC V V V V V NC NC ZZ H DD SS SS SS DD J DQB NC V V V V V V V DQA NC J DDQ DD SS SS SS DD DDQ K DQB NC V V V V V V V DQA NC K DDQ DD SS SS SS DD DDQ L DQB NC V V V V V V V DQA NC L DDQ DD SS SS SS DD DDQ M DQB NC V V V V V V V DQA NC M DDQ DD SS SS SS DD DDQ N DQPB NC V V NC A NC V V NC NC N DDQ SS SS DDQ P NC NC A A TDI A1 TDO A A A A P R LBO A19 A A TMS A0 TCK A A A A R 11 x 15 Bump BGA13 mm x 15 mm Body1.0 mm Bump Pitch Rev: 1.03 8/2013 2/32 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see