GS832118/32/36AD-xxxV 333 MHz150 MHz 165-Bump BGA 2M x 18, 1M x 32, 1M x 36 2.5 V or 3.3 V V Commercial Temp DD 36Mb Sync Burst SRAMs Industrial Temp 2.5 V or 3.3 V I/O Flow Through/Pipeline Reads Features The function of the Data Output register can be controlled by IEEE 1149.1 JTAG-compatible Boundary Scan the user via the FT mode pin (Pin 14). Holding the FT mode 1.8 V or 2.5 V core power supply pin low places the RAM in Flow Through mode, causing 1.8 V or 2.5 V I/O supply output data to bypass the Data Output Register. Holding FT LBO pin for Linear or Interleaved Burst mode high places the RAM in Pipeline mode, activating the rising- Internal input resistors on mode pins allow floating mode pins edge-triggered Data Output Register. Byte Write (BW) and/or Global Write (GW) operation Internal self-timed write cycle SCD Pipelined Reads Automatic power-down for portable applications The GS832118/32/36AD-xxxV is a SCD (Single Cycle JEDEC-standard 165-bump BGA package Deselect) pipelined synchronous SRAM. DCD (Dual Cycle RoHS-compliant 165-bump BGA package available Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD Functional Description RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Applications The GS832118/32/36AD-xxxV is a 37,748,736-bit high Byte Write and Global Write performance synchronous SRAM with a 2-bit burst address Byte write operation is performed by using Byte Write enable counter. Although of a type originally developed for Level 2 (BW) input combined with one or more individual byte write Cache applications supporting high performance CPUs, the signals (Bx). In addition, Global Write (GW) is available for device now finds application in synchronous SRAM writing all bytes at one time, regardless of the Byte Write applications, ranging from DSP main store to networking chip control inputs. set support. Sleep Mode Controls Low power (Sleep mode) is attained through the assertion Addresses, data I/Os, chip enable (E1), address burst control (High) of the ZZ signal, or by stopping the clock (CK). inputs (ADSP, ADSC, ADV) and write control inputs (Bx, Memory data is retained during Sleep mode. BW, GW) are synchronous and are controlled by a positive- Core and Interface Voltages edge-triggered clock input (CK). Output enable (G) and power The GS832118/32/36AD-xxxV operates on a 1.8 V or 2.5 V down control (ZZ) are asynchronous inputs. Burst cycles can power supply. All inputs are 1.8 V or 2.5 V compatible. be initiated with either ADSP or ADSC inputs. In Burst mode, Separate output power (V ) pins are used to decouple DDQ subsequent burst addresses are generated internally and are output noise from the internal circuits and are 1.8 V or 2.5 V controlled by ADV. The burst address counter may be compatible. configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Parameter Synopsis -333 -250 -200 -150 Unit t 3.0 3.0 3.0 3.8 ns KQ 3.0 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 365 290 250 215 mA Curr (x32/x36) 425 345 290 240 mA t 5.0 5.5 6.5 7.5 ns KQ Flow 5.0 5.5 6.5 7.5 ns tCycle Through Curr (x18) 270 245 210 200 mA 2-1-1-1 Curr (x32/x36) 315 280 250 230 mA Rev: 1.03 8/2013 1/30 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS832118/32/36AD-xxxV 165 Bump BGAx18 Commom I/OTop View (Package D) 1 2 3 4 5 6 7 8 9 10 11 A NC A E1 BB NC E3 BW ADSC ADV A A A B NC A E2 NC BA CK GW G ADSP A NC B C NC NC V V V V V V V NC DQPA C DDQ SS SS SS SS SS DDQ D NC DQB V V V V V V V NC DQA D DDQ DD SS SS SS DD DDQ E NC DQB V V V V V V V NC DQA E DDQ DD SS SS SS DD DDQ F NC DQB V V V V V V V NC DQA F DDQ DD SS SS SS DD DDQ G NC DQB V V V V V V V NC DQA G DDQ DD SS SS SS DD DDQ H FT MCL NC V V V V V NC NC ZZ H DD SS SS SS DD J DQB NC V V V V V V V DQA NC J DDQ DD SS SS SS DD DDQ K DQB NC V V V V V V V DQA NC K DDQ DD SS SS SS DD DDQ L DQB NC V V V V V V V DQA NC L DDQ DD SS SS SS DD DDQ M DQB NC V V V V V V V DQA NC M DDQ DD SS SS SS DD DDQ N DQPB NC V V NC A NC V V NC NC N DDQ SS SS DDQ P NC NC A A TDI A1 TDO A A A A P R LBO A19 A A TMS A0 TCK A A A A R 11 x 15 Bump BGA13 mm x 15 mm Body1.0 mm Bump Pitch Rev: 1.03 8/2013 2/30 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see