GS8321Z18/32/36AD-400/375/333/250/200/150 400 MHz150 MHz 165-Bump BGA 36Mb Pipelined and Flow Through 2.5 V, or 3.3 V V DD Commercial Temp Synchronous NBT SRAM 2.5 V, or 3.3 V I/O Industrial Temp Because it is a synchronous device, address, data inputs, and Features read/ write control inputs are captured on the rising edge of the User-configurable Pipeline and Flow Through mode input clock. Burst order control (LBO) must be tied to a power NBT (No Bus Turn Around) functionality allows zero wait rail for proper operation. Asynchronous inputs include the read-write-read bus utilization Sleep mode enable, ZZ and Output Enable. Output Enable can Fully pin-compatible with both pipelined and flow through be used to override the synchronous control of the output NtRAM, NoBL and ZBT SRAMs drivers and turn the RAM s output drivers off at any time. IEEE 1149.1 JTAG-compatible Boundary Scan Write cycles are internally self-timed and initiated by the rising 2.5 V, or 3.3 V +10%/10% core power supply edge of the clock input. This feature eliminates complex off- LBO pin for Linear or Interleave Burst mode chip write pulse generation required by asynchronous SRAMs Pin-compatible with 2Mb, 4Mb, 8Mb, and 18Mb devices and simplifies input signal timing. Byte write operation (9-bit Bytes) 3 chip enable signals for easy depth expansion The GS8321Z18/32/36AD may be configured by the user to ZZ pin for automatic power-down operate in Pipeline or Flow Through mode. Operating as a JEDEC-standard 165-bump BGA package pipelined synchronous device, in addition to the rising-edge- RoHS-compliant 165-bump BGA package available triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read Functional Description cycles, pipelined SRAM output data is temporarily stored by The GS8321Z18/32/36AD is a 36Mbit Synchronous Static the edge triggered output register during the access cycle and SRAM. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL or then released to the output drivers at the next rising edge of other pipelined read/double late write or flow through read/ clock. single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles The GS8321Z18/32/36AD is implemented with GSI s high when the device is switched from read to write cycles. performance CMOS technology and is available in JEDEC- standard 165-bump BGA package. Parameter Synopsis -400 -375 -333 -250 -200 -150 Unit t 2.5 2.5 2.5 2.5 3.0 3.8 ns KQ 2.5 2.66 3.3 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 395 390 355 280 240 205 mA Curr (x32/x36) 475 455 415 335 280 230 mA t 4.0 4.2 4.5 5.5 6.5 7.5 ns KQ Flow 4.0 4.2 4.5 5.5 6.5 7.5 ns tCycle Through Curr (x18) 290 275 260 235 200 190 mA 2-1-1-1 Curr (x32/x36) 335 320 305 270 240 220 mA Rev: 1.03 8/2013 1/34 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8321Z18/32/36AD-400/375/333/250/200/150 165 Bump BGAx18 Commom I/OTop View (Package D) 1 2 3 4 5 6 7 8 9 10 11 A NC A E1 BB NC E3 CKE ADV A A A A B NC A E2 NC BA CK W G A A NC B C NC NC V V V V V V V NC DQA C DDQ SS SS SS SS SS DDQ D NC DQB V V V V V V V NC DQA D DDQ DD SS SS SS DD DDQ E NC DQB V V V V V V V NC DQA E DDQ DD SS SS SS DD DDQ F NC DQB V V V V V V V NC DQA F DDQ DD SS SS SS DD DDQ G NC DQB V V V V V V V NC DQA G DDQ DD SS SS SS DD DDQ H FT MCH NC V V V V V NC NC ZZ H DD SS SS SS DD J DQB NC V V V V V V V DQA NC J DDQ DD SS SS SS DD DDQ K DQB NC V V V V V V V DQA NC K DDQ DD SS SS SS DD DDQ L DQB NC V V V V V V V DQA NC L DDQ DD SS SS SS DD DDQ M DQB NC V V V V V V V DQA NC M DDQ DD SS SS SS DD DDQ N DQB NC V V NC NC NC V V NC NC N DDQ SS SS DDQ P NC NC A A TDI A1 TDO A A A NC P R LBO A A A TMS A0 TCK A A A A R 11 x 15 Bump BGA13 mm x 15 mm Body1.0 mm Bump Pitch Rev: 1.03 8/2013 2/34 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see