GS832272(C) 209-Pin BGA 250 MHz133 MHz 512K x 72 Commercial Temp 2.5 V or 3.3 V V DD 36Mb S/DCD Sync Burst SRAMs Industrial Temp 2.5 V or 3.3 V I/O either linear or interleave order with the Linear Burst Order (LBO) Features input. The Burst function need not be used. New addresses can be FT pin for user-configurable flow through or pipeline operation Single/Dual Cycle Deselect selectable loaded on every cycle with no degradation of chip performance. IEEE 1149.1 JTAG-compatible Boundary Scan Flow Through/Pipeline Reads ZQ mode pin for user-selectable high/low output drive The function of the Data Output register can be controlled by the 2.5 V +10%/10% core power supply user via the FT mode . Holding the FT mode pin low places the 3.3 V +10%/10% core power supply RAM in Flow Through mode, causing output data to bypass the 2.5 V or 3.3 V I/O supply Data Output Register. Holding FT high places the RAM in LBO pin for Linear or Interleaved Burst mode Pipeline mode, activating the rising-edge-triggered Data Output Internal input resistors on mode pins allow floating mode pins Register. Default to SCD x18/x36 Interleaved Pipeline mode SCD and DCD Pipelined Reads Byte Write (BW) and/or Global Write (GW) operation The GS832272 is a SCD (Single Cycle Deselect) and DCD (Dual Internal self-timed write cycle Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs Automatic power-down for portable applications pipeline disable commands to the same degree as read commands. JEDEC-standard 209-bump BGA package SCD SRAMs pipeline deselect commands one stage less than read RoHS-compliant package available commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the Functional Description input registers. DCD RAMs hold the deselect command for one Applications full cycle and then begin turning off their outputs just after the The GS832272 is a 37,748,736-bit high performance synchronous second rising edge of clock. The user may configure this SRAM SRAM with a 2-bit burst address counter. Although of a type for either mode of operation using the SCD mode input. originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in Byte Write and Global Write synchronous SRAM applications, ranging from DSP main store to Byte write operation is performed by using Byte Write enable networking chip set support. (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for Controls writing all bytes at one time, regardless of the Byte Write control Addresses, data I/Os, chip enable (E1), address burst control inputs. inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge- FLXDrive triggered clock input (CK). Output enable (G) and power down The ZQ pin allows selection between high drive strength (ZQ low) control (ZZ) are asynchronous inputs. Burst cycles can be initiated for multi-drop bus applications and normal drive strength (ZQ with either ADSP or ADSC inputs. In Burst mode, subsequent floating or high) point-to-point applications. See the Output Driver burst addresses are generated internally and are controlled by Characteristics chart for details. ADV. The burst address counter may be configured to count in Parameter Synopsis -250 -225 -200 -166 -150 -133 Unit tt (x72) 3.0 3.0 3.0 3.5 3.8 4.0 ns KQ Pipeline 4.0 4.4 5.0 6.0 6.7 7.5 ns tCycle 3-1-1-1 Curr (x72) 440 410 370 320 300 265 mA t 6.5 7.0 7.5 8.0 8.5 8.5 ns Flow KQ 6.5 7.0 7.5 8.0 8.5 8.5 ns Through tCycle 2-1-1-1 Curr (x72) 315 295 265 255 240 230 mA Rev: 1.08 10/2014 1/33 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS832272(C) 209-Bump BGAx72 Common I/OTop View (Package C) 1 2 3 4 5 6 7 8 9 10 11 A DQG DQG A E2 ADSP ADSC ADV E3 A DQB DQB A B DQG DQG BC BG NC BW A BB BF DQB DQB B C DQG DQG BH BD NC E1 NC BE BA DQB DQB C V V D DQG DQG NC NC G GW NC DQB DQB D SS SS V V V V V V V E DQPG DQPC DQPF DQPB E DDQ DDQ DD DD DD DDQ DDQ V V V V V V F DQC DQC ZQ DQF DQF F SS SS SS SS SS SS V V V V V V G DQC DQC MCH DQF DQF G DDQ DDQ DD DD DDQ DDQ V V V V V H DQC DQC MCL V DQF DQF H SS SS SS SS SS SS V V V V V V J DQC DQC MCL DQF DQF J DDQ DDQ DD DD DDQ DDQ V V K NC NC CK NC MCL NC NC NC NC K SS SS V V V V V V L DQH DQH FT DQA DQA L DDQ DDQ DD DD DDQ DDQ V V V V V V M DQH DQH MCL DQA DQA M SS SS SS SS SS SS V V V V V V N DQH DQH SCD DQA DQA N DDQ DDQ DD DD DDQ DDQ V V V V V V P DQH DQH ZZ DQA DQA P SS SS SS SS SS SS V V V V V V V R DQPD DQPH DQPA DQPE R DDQ DDQ DD DD DD DDQ DDQ V V T DQD DQD NC NC LBO NC NC DQE DQE T SS SS U DQD DQD NC A A A A A A DQE DQE U V DQD DQD A A A A1 A A A DQE DQE V W DQD DQD TMS TDI A A0 A TDO TCK DQE DQE W 2 11 x 19 Bump BGA14 x 22 mm Body1 mm Bump Pitch Rev: 1.08 10/2014 2/33 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see