GS8322Z18/36A(B/D)-xxxV 333 MHz150 MHz 119 & 165 BGA 36Mb Pipelined and Flow Through 1.8 V or 2.5 V V Commercial Temp DD Synchronous NBT SRAM Industrial Temp 1.8 V or 2.5 V I/O Features Because it is a synchronous device, address, data inputs, and NBT (No Bus Turn Around) functionality allows zero wait read/write control inputs are captured on the rising edge of the Read-Write-Read bus utilization fully pin-compatible with input clock. Burst order control (LBO) must be tied to a power both pipelined and flow through NtRAM, NoBL and rail for proper operation. Asynchronous inputs include the ZBT SRAMs Sleep mode enable (ZZ) and Output Enable. Output Enable can 1.8 V or 2.5 V core power supply be used to override the synchronous control of the output 1.8 V or 2.5 V I/O supply drivers and turn the RAM s output drivers off at any time. User-configurable Pipeline and Flow Through mode Write cycles are internally self-timed and initiated by the rising ZQ mode pin for user-selectable high/low output drive edge of the clock input. This feature eliminates complex off- IEEE 1149.1 JTAG-compatible Boundary Scan chip write pulse generation required by asynchronous SRAMs LBO pin for Linear or Interleave Burst mode and simplifies input signal timing. Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices Byte write operation (9-bit Bytes) The GS8322Z18/36A-xxxV may be configured by the user to 3 chip enable signals for easy depth expansion operate in Pipeline or Flow Through mode. Operating as a ZZ Pin for automatic power-down pipelined synchronous device, in addition to the rising-edge- JEDEC-standard 119- and 165-Bump BGA package triggered registers that capture input signals, the device RoHS-compliant packages available incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by Functional Description the edge-triggered output register during the access cycle and The GS8322Z18/36A-xxxV is a 36Mbit Synchronous Static then released to the output drivers at the next rising edge of SRAM. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL or clock. other pipelined read/double late write or flow through read/ The GS8322Z18/36A-xxxV is implemented with GSI s high single late write SRAMs, allow utilization of all available bus performance CMOS technology and is available in a JEDEC- bandwidth by eliminating the need to insert deselect cycles standard 119-bump or 165-bump BGA package. when the device is switched from read to write cycles. Parameter Synopsis -333 -250 -200 -150 Unit t 3.0 3.0 3.0 3.8 ns KQ 3.0 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 365 290 250 215 mA Curr (x36) 425 345 290 240 mA t 5.0 5.5 6.5 7.5 ns KQ Flow 5.0 5.5 6.5 7.5 ns tCycle Through Curr (x18) 270 245 210 200 mA 2-1-1-1 Curr (x36) 315 280 250 230 mA Rev: 1.03a 12/2020 1/35 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8322Z18/36A(B/D)-xxxV GS8322Z36AB-xxxV Pad Out119-Bump BGATop View (Package B) 1 2 3 4 5 6 7 V V A A A A A A A DDQ DDQ B NC E2 A ADV A E3 NC B V C NC A A A A NC C DD V V D DQC D Q PC ZQ D Q PB DQB D SS SS V V E DQC DQC E1 DQB DQB E SS SS F V DQC V G V DQB V F DDQ SS SS DDQ G DQC DQC BC A BB DQB DQB G V V H DQC DQC W DQB DQB H SS SS V V V V V J NC NC J DDQ DD DD DD DDQ V V K DQD DQD CK DQA DQA K SS SS L DQD DQD BD NC BA DQA DQA L V V V V M DQD CKE DQA M DDQ SS SS DDQ V V N DQD DQD A1 DQA DQA N SS SS V V P DQD D Q PD A0 D Q PA DQA P SS SS V R NC A LBO FT A NC R DD T NC NC A A A A ZZ T V V U TMS TDI TCK TDO NC U DDQ DDQ 2 7 x 17 Bump BGA14 x 22 mm Body1.27 mm Bump Pitch Rev: 1.03a 12/2020 2/35 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see