GS8342T07/10/19/37BD-450/400/350/333/300 TM 450 MHz300 MHz 165-Bump BGA 36Mb SigmaDDR-II+ 1.8 V V Commercial Temp DD Burst of 2 SRAM Industrial Temp 1.8 V or 1.5 V I/O The GS8342T07/10/19/37BD SigmaDDR-II+ SRAMs are just Features one element in a family of low power, low voltage HSTL I/O 2.0 Clock Latency SRAMs designed to operate at the speeds needed to implement Simultaneous Read and Write SigmaDDR Interface economical high performance networking systems. Common I/O bus JEDEC-standard pinout and package Double Data Rate interface Clocking and Addressing Schemes Byte Write controls sampled at data-in time Burst of 2 Read and Write The GS8342T07/10/19/37BD SigmaDDR-II+ SRAMs are On-Die Termination (ODT) on Data (D), Byte Write (BW), synchronous devices. They employ two input register clock and Clock (K, K) inputs inputs, K and K. K and K are independent single-ended clock 1.8 V +100/100 mV core power supply inputs, not differential inputs to a single differential clock input 1.5 V or 1.8 V HSTL Interface buffer. Pipelined read operation with self-timed Late Write Fully coherent read and write pipelines Each internal read and write operation in a SigmaDDR-II+ B2 ZQ pin for programmable output drive strength RAM is two times wider than the device I/O bus. An input data Data Valid pin (QVLD) Support bus de-multiplexer is used to accumulate incoming data before IEEE 1149.1 JTAG-compliant Boundary Scan it is simultaneously written to the memory array. An output 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package data multiplexer is used to capture the data produced from a RoHS-compliant 165-bump BGA package available single memory array read and then route it to the appropriate output drivers as needed. Therefore the address field of a SigmaDDR-II+ B2 RAM is always one address pin less than SigmaDDR Family Overview the advertised index depth (e.g., the 4M x 8 has a 2M The GS8342T07/10/19/37BD are built in compliance with the addressable index). SigmaDDR-II+ SRAM pinout standard for Common I/O synchronous SRAMs. They are 37,748,736 (36Mb) SRAMs. Parameter Synopsis -450 -400 -350 -333 -300 tKHKH 2.22 ns 2.5 ns 2.86 ns 3.0 ns 3.3 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns Rev: 1.02a 8/2017 1/29 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8342T07/10/19/37BD-450/400/350/333/300 4M x 8 SigmaDDR-II+ SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 NC/SA NC/SA A CQ SA R/W NW1 K LD SA SA CQ (72Mb) (144Mb) NC/SA B NC NC NC SA K NW0 SA NC NC DQ3 (288Mb) C NC NC NC V SA SA SA V NC NC NC SS SS D NC NC NC V V V V V NC NC NC SS SS SS SS SS E NC NC DQ4 V V V V V NC NC DQ2 DDQ SS SS SS DDQ F NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ G NC NC DQ5 V V V V V NC NC NC DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC NC V V V V V NC DQ1 NC DDQ DD SS DD DDQ K NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ L NC DQ6 NC V V V V V NC NC DQ0 DDQ SS SS SS DDQ M NC NC NC V V V V V NC NC NC SS SS SS SS SS N NC NC NC V SA SA SA V NC NC NC SS SS P NC NC DQ7 SA SA QVLD SA SA NC NC NC R TDO TCK SA SA SA ODT SA SA SA TMS TDI 11 x 15 Bump BGA13 x 15 mm Body1 mm Bump Pitch Notes: 1. NW0 controls writes to DQ0:DQ3 NW1 controls writes to DQ4:DQ7. 2. Pins A2, A7, and B5 are the expansion addresses. Rev: 1.02a 8/2017 2/29 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see