GS8342TT07/10/19/37BD-450/400/350/333/300 TM 450 MHz300 MHz 165-Bump BGA 36Mb SigmaDDR-II+ 1.8 V V Commercial Temp DD Burst of 2 SRAM Industrial Temp 1.8 V or 1.5 V I/O Features 2.0 Clock Latency Simultaneous Read and Write SigmaDDR Interface Common I/O bus JEDEC-standard pinout and package Double Data Rate interface Byte Write controls sampled at data-in time Burst of 2 Read and Write Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs 1.8 V +100/100 mV core power supply 1.5 V or 1.8 V HSTL Interface Pipelined read operation with self-timed Late Write Fully coherent read and write pipelines ZQ pin for programmable output drive strength Bottom View Data Valid pin (QVLD) Support 165-Bump, 13 mm x 15 mm BGA IEEE 1149.1 JTAG-compliant Boundary Scan 1 mm Bump Pitch, 11 x 15 Bump Array 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package RoHS-compliant 165-bump BGA package available SigmaDDR Family Overview Clocking and Addressing Schemes The GS8342TT07/10/19/37BD are built in compliance with The GS8342TT07/10/19/37BD SigmaDDR-II+ SRAMs are the SigmaDDR-II+ SRAM pinout standard for Common I/O synchronous devices. They employ two input register clock synchronous SRAMs. They are 37,748,736 (36Mb) SRAMs. inputs, K and K. K and K are independent single-ended clock The GS8342TT07/10/19/37BD SigmaDDR-II+ SRAMs are inputs, not differential inputs to a single differential clock input just one element in a family of low power, low voltage HSTL buffer. I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Because Common I/O SigmaDDR-II+ RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a SigmaDDR-II+ B2 RAM is always one address pin less than the advertised index depth force return (e.g., the 2M x 18 has a 1M addressable index). Parameter Synopsis -450 -400 -350 -333 -300 tKHKH 2.22 ns 2.5 ns 2.86 ns 3.0 ns 3.3 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns Rev: 1.01a 8/2017 1/30 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8342TT07/10/19/37BD-450/400/350/333/300 4M x 8 SigmaDDR-II+ SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 NC/SA NC/SA A CQ SA R/W NW1 K LD SA SA CQ (72Mb) (144Mb) NC/SA B NC NC NC SA K NW0 SA NC NC DQ3 (288Mb) C NC NC NC V SA SA SA V NC NC NC SS SS D NC NC NC V V V V V NC NC NC SS SS SS SS SS E NC NC DQ4 V V V V V NC NC DQ2 DDQ SS SS SS DDQ F NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ G NC NC DQ5 V V V V V NC NC NC DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC NC V V V V V NC DQ1 NC DDQ DD SS DD DDQ K NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ L NC DQ6 NC V V V V V NC NC DQ0 DDQ SS SS SS DDQ M NC NC NC V V V V V NC NC NC SS SS SS SS SS N NC NC NC V SA SA SA V NC NC NC SS SS P NC NC DQ7 SA SA QVLD SA SA NC NC NC R TDO TCK SA SA SA ODT SA SA SA TMS TDI 11 x 15 Bump BGA13 x 15 mm Body1 mm Bump Pitch Notes: 1. NW0 controls writes to DQ0:DQ3 NW1 controls writes to DQ4:DQ7. 2. Pins A2, A7, and B5 are the expansion addresses. Rev: 1.01a 8/2017 2/30 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see