GS84018/32/36CB-250/200/166/150
BGA 250 MHz150 MHz
256K x 18, 128K x 32, 128K x 36
Commercial Temp 3.3 V V
DD
4Mb Sync Burst SRAMs
Industrial Temp
3.3 V and 2.5 V I/O
internally and are controlled by ADV. The burst address
Features
counter may be configured to count in either linear or
FT pin for user-configurable flow through or pipelined
interleave order with the Linear Burst Order (LBO) input. The
operation
burst function need not be used. New addresses can be loaded
Single Cycle Deselect (SCD) operation
on every cycle with no degradation of chip performance.
3.3 V +10%/5% core power supply
2.5 V or 3.3 V I/O supply Flow Through/Pipeline Reads
LBO pin for Linear or Interleaved Burst mode The function of the Data Output register can be controlled by
Internal input resistors on mode pins allow floating mode pins the user via the FT mode pin/bump (pin 14 in the TQFP and
Default to Interleaved Pipelined mode bump 5R in the BGA). Holding the FT mode pin/bump low
Byte Write (BW) and/or Global Write (GW) operation places the RAM in Flow Through mode, causing output data to
Common data inputs and data outputs bypass the Data Output Register. Holding FT high places the
Clock control, registered, address, data, and control RAM in Pipelined mode, activating the rising-edge-triggered
Internal self-timed write cycle Data Output Register.
Automatic power-down for portable applications
SCD Pipelined Reads
JEDEC-standard 119-bump BGA package
The GS84018/32/36C is an SCD (Single Cycle Deselect)
RoHS-compliant 119-bump BGA package
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
Functional Description
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
Applications
command has been captured in the input registers.
The GS84018/32/36C is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2-
Byte Write and Global Write
bit burst address counter. Although of a type originally
Byte write operation is performed by using byte write enable
developed for Level 2 Cache applications supporting high
(BW) input combined with one or more individual byte write
performance CPUs, the device now finds application in
signals (Bx). In addition, Global Write (GW) is available for
synchronous SRAM applications ranging from DSP main store
writing all bytes at one time, regardless of the Byte Write
to networking chip set support. The GS84018/32/36A is
control inputs.
available in a JEDEC standard 100-lead TQFP or 119-Bump
Sleep Mode
BGA package.
Low power (Sleep mode) is attained through the assertion
Controls
(High) of the ZZ signal, or by stopping the clock (CK).
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
Memory data is retained during Sleep mode.
control inputs (ADSP, ADSC, ADV), and write control inputs
Core and Interface Voltages
(Bx, BW, GW) are synchronous and are controlled by a
The GS84018/32/36C operates on a 3.3 V power supply and all
positive-edge-triggered clock input (CK). Output enable (G)
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
and power down control (ZZ) are asynchronous inputs. Burst
output power (V ) pins are used to de-couple output noise
cycles can be initiated with either ADSP or ADSC inputs. In DDQ
from the internal circuit.
Burst mode, subsequent burst addresses are generated
Parameter Synopsis
250 200 166 150 Unit
tCycle 4.0 5.5 6.0 6.7 ns
KQ 2.5 3.0 3.5 3.8 ns
Pipeline t
3-1-1-1 Curr (X18) 195 170 150 140 MHz
Curr (X32/X36) 225 195 185 160 MHz
tKQ 5.5 6.5 7.0 7.5
Flow ns
tCycle 5.5 6.5 7.0 7.5
Through ns
(X18) 160 140 140 128
Curr
2-1-1-1 MHz
Curr (X32/X36) 180 160 155 145
Rev: 1.01 9/2014 1/23 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see GS84018/32/36CB-250/200/166/150
GS84018C Pad Out119-Bump BGATop View (Package B)
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A V A A ADSP AA V
DDQ DDQ
B NC E2 AADSC AE3 NC
C NC A A V AA NC
DD
D DQB NC V NC V DQPA NC
SS SS
NC DQB V E1 V NC DQA
E
SS SS
F V NC V G V DQA V
DDQ SS SS DDQ
G NC DQB BB ADV NC NC DQA
H DQB NC V GW V DQA NC
SS SS
J V V NC V NC V V
DDQ DD DD DD DDQ
NC DQB V CK V NC DQA
K
SS SS
L DQB NC NC NC BA DQA NC
M V DQB V BW V NC V
DDQ SS SS DDQ
N DQB NC V A1 V DQA NC
SS SS
P NC DQPB V A0 V NC DQA
SS SS
NC A LBO V FT ANC
R
DD
T NC A A NC A A ZZ
U V NC NC NC NC NC V
DDQ DDQ
Rev: 1.01 9/2014 2/23 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see