GS84018/32/36CGT-250/200/166/150 TQFP 250 MHz150 MHz 256K x 18, 128K x 32, 128K x 36 Commercial Temp 3.3 V V DD 4Mb Sync Burst SRAMs Industrial Temp 3.3 V and 2.5 V I/O counter may be configured to count in either linear or Features interleave order with the Linear Burst Order (LBO) input. The FT pin for user-configurable flow through or pipelined burst function need not be used. New addresses can be loaded operation on every cycle with no degradation of chip performance. Single Cycle Deselect (SCD) operation 3.3 V 10% core power supply Flow Through/Pipeline Reads 2.5 V or 3.3 V I/O supply The function of the Data Output register can be controlled by LBO pin for Linear or Interleaved Burst mode the user via the FT mode pin/bump (pin 14 in the TQFP and Internal input resistors on mode pins allow floating mode pins bump 5R in the BGA). Holding the FT mode pin/bump low Default to Interleaved Pipelined mode places the RAM in Flow Through mode, causing output data to Byte Write (BW) and/or Global Write (GW) operation bypass the Data Output Register. Holding FT high places the Common data inputs and data outputs RAM in Pipelined mode, activating the rising-edge-triggered Clock control, registered, address, data, and control Data Output Register. Internal self-timed write cycle SCD Pipelined Reads Automatic power-down for portable applications The GS84018/32/36CGT is an SCD (Single Cycle Deselect) RoHS-compliant 100-lead TQFP package pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect Functional Description commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect Applications command has been captured in the input registers. The GS84018/32/36CGT is a 4,718,592-bit (4,194,304-bit for x32 version) high performance synchronous SRAM with a 2- Byte Write and Global Write bit burst address counter. Although of a type originally Byte write operation is performed by using byte write enable developed for Level 2 Cache applications supporting high (BW) input combined with one or more individual byte write performance CPUs, the device now finds application in signals (Bx). In addition, Global Write (GW) is available for synchronous SRAM applications ranging from DSP main store writing all bytes at one time, regardless of the Byte Write to networking chip set support. The GS84018/32/36CGT is control inputs. available in a JEDEC standard 100-lead TQFP package. Sleep Mode Controls Low power (Sleep mode) is attained through the assertion Addresses, data I/Os, chip enables (E1, E2, E3), address burst (High) of the ZZ signal, or by stopping the clock (CK). control inputs (ADSP, ADSC, ADV), and write control inputs Memory data is retained during Sleep mode. (Bx, BW, GW) are synchronous and are controlled by a Core and Interface Voltages positive-edge-triggered clock input (CK). Output enable (G) The GS84018/32/36CGT operates on a 3.3 V power supply and power down control (ZZ) are asynchronous inputs. Burst and all inputs/outputs are 3.3 V- and 2.5 V-compatible. cycles can be initiated with either ADSP or ADSC inputs. In Separate output power (V ) pins are used to de-couple Burst mode, subsequent burst addresses are generated DDQ output noise from the internal circuit. internally and are controlled by ADV. The burst address Parameter Synopsis -250 -200 -166 -150 Unit t 2.5 3.0 3.0 3.8 ns KQ 4.0 5.0 5.0 6.7 ns tCycle Pipeline 3-1-1-1 Curr (x18) 195 170 160 140 mA Curr (x32/x36) 225 195 185 160 mA t 5.5 6.5 6.5 7.5 ns KQ 5.5 6.5 6.5 7.5 ns Flow Through tCycle 2-1-1-1 Curr (x18) 160 140 135 128 mA Curr (x32/x36) 180 160 155 145 mA Rev: 1.01a 6/2017 1/22 2014, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS84018/32/36CGT-250/200/166/150 GS84018C 100-Pin TQFP Pinout (Package GT) 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 256K x 18 V V 10 71 SS SS VDDQ V 11 Top View 70 DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 FT 67 SS NC V 15 66 DD VDD NC 16 65 ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V VDDQ 20 61 DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS VDDQ 27 54 V DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either V or V . These pins can also be left floating. DD SS Rev: 1.01a 6/2017 2/22 2014, GSI Technology Specifications cited are subject to change without notice. For latest documentation see