GS840Z18CGT/GS840Z36CGT 250 MHz100 MHz 100-Pin TQFP 4Mb Pipelined and Flow Through 3.3 V V DD Commercial Temp 2.5 V and 3.3 V V Synchronous NBT SRAMs DDQ Industrial Temp Because it is a synchronous device, address, data inputs, and Features read/ write control inputs are captured on the rising edge of the 256K x 18 and 128K x 36 configurations input clock. Burst order control (LBO) must be tied to a power User configurable Pipeline and Flow Through mode rail for proper operation. Asynchronous inputs include the NBT (No Bus Turn Around) functionality allows zero wait sleep mode enable (ZZ) and Output Enable. Output Enable can read-write-read bus utilization be used to override the synchronous control of the output Fully pin compatible with both pipelined and flow through drivers and turn the RAM s output drivers off at any time. NtRAM, NoBL and ZBT SRAMs Write cycles are internally self-timed and initiated by the rising Pin-compatible with 2Mb, 9Mb and 18Mb devices edge of the clock input. This feature eliminates complex off- 3.3 V +10%/5% core power supply chip write pulse generation required by asynchronous SRAMs 2.5 V or 3.3 V I/O supply and simplifies input signal timing. LBO pin for Linear or Interleave Burst mode Byte write operation (9-bit Bytes) The GS840Z18/36CGT may be configured by the user to 3 chip enable signals for easy depth expansion operate in Pipeline or Flow Through mode. Operating as a Clock Control, registered address, data, and control pipelined synchronous device, in addition to the rising-edge- ZZ Pin for automatic power-down triggered registers that capture input signals, the device RoHS-compliant 100-lead TQFP package incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by Functional Description the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of The GS840Z18/36CGT is a 4Mbit Synchronous Static SRAM. clock. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single The GS840Z18/36CGT is implemented with GSI s high late write SRAMs, allow utilization of all available bus performance CMOS technology and is available in a 6/6 bandwidth by eliminating the need to insert deselect cycles RoHS-compliant, JEDEC-standard 100-pin TQFP package. when the device is switched from read to write cycles. Parameter Synopsis 250 200 166 150 100 tCycle 4.0 ns 5.5 ns 6.0 ns 6.7 ns 10 ns Pipeline tKQ 2.5 ns 3.0 ns 3.5 ns 3.8 ns 4.5 ns 3-1-1-1 IDD TBD TBD TBD TBD TBD Flow tKQ 5.5 ns 6.5 ns 7.0 ns 7.5 ns 12 ns tCycle 5.5 ns 6.5 ns 7.0 ns 7.5 ns 12 ns Through 2-1-1-1 IDD TBD TBD TBD TBD TBD Rev: 1.01 8/2011 1/22 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS840Z18CGT/GS840Z36CGT GS840Z18CGT Pinout (Package T) 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 256K x 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 FT 67 SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 DQA DQB 23 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.01 8/2011 2/22 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see