GS842Z18CB/GS842Z36CB 250 MHz100 MHz 119-Bump BGA 4Mb Pipelined and Flow Through 3.3 V V DD Commercial Temp 2.5 V and 3.3 V V Synchronous NBT SRAMs DDQ Industrial Temp Because it is a synchronous device, address, data inputs, and Features read/ write control inputs are captured on the rising edge of the 256K x 18 and 128K x 36 configurations input clock. Burst order control (LBO) must be tied to a power User configurable Pipeline and Flow Through mode rail for proper operation. Asynchronous inputs include the NBT (No Bus Turn Around) functionality allows zero wait sleep mode enable (ZZ) and Output Enable. Output Enable can read-write-read bus utilization be used to override the synchronous control of the output Fully pin compatible with both pipelined and flow through drivers and turn the RAM s output drivers off at any time. NtRAM, NoBL and ZBT SRAMs Write cycles are internally self-timed and initiated by the rising Pin-compatible with 2Mb, 9Mb, and 18Mb devices edge of the clock input. This feature eliminates complex off- 3.3 V +10%/10% core power supply chip write pulse generation required by asynchronous SRAMs 2.5 V or 3.3 V I/O supply and simplifies input signal timing. LBO pin for Linear or Interleave Burst mode Byte write operation (9-bit Bytes) The GS842Z18/36CB may be configured by the user to operate 3 chip enable signals for easy depth expansion in Pipeline or Flow Through mode. Operating as a pipelined Clock Control, registered address, data, and control synchronous device, in addition to the rising-edge-triggered ZZ Pin for automatic power-down registers that capture input signals, the device incorporates a JEDEC-standard 119-bump BGA package rising-edge-triggered output register. For read cycles, pipelined RoHS-compliant package available SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the Functional Description output drivers at the next rising edge of clock. The GS842Z18/36CB is a 4Mbit Synchronous Static SRAM. The GS842Z18/36CB is implemented with GSI s high GSI s NBT SRAMs, like ZBT, NtRAM, NoBL or other performance CMOS technology and is available in a JEDEC- pipelined read/double late write or flow through read/single standard 119-bump BGA package. late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Parameter Synopsis 250 200 166 150 100 tCycle 4.0 ns 5.5 ns 6.0 ns 6.7 ns 10 ns Pipeline tKQ 2.5 ns 3.0 ns 3.5 ns 3.8 ns 4.5 ns 3-1-1-1 IDD TBD TBD TBD TBD TBD Flow tKQ 5.5 ns 6.5 ns 7.0 ns 7.5 ns 12 ns tCycle 5.5 ns 6.5 ns 7.0 ns 7.5 ns 12 ns Through 2-1-1-1 IDD TBD TBD TBD TBD TBD Rev: 1.01 8/2011 1/29 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS842Z18CB/GS842Z36CB GS842Z18C Pad Out119-Bump BGATop View (Packge B) 1234567 A V AA NC AA V DDQ DDQ B NC E2 AADV A E3 NC C NC A A V AA NC DD D DQB NC V ZQ V DQPA NC SS SS E NC DQB V E1 V NC DQA SS SS F V NC V G V DQA V DDQ SS SS DDQ G NC DQB BB NC NC NC DQA H DQB NC V W V DQA NC SS SS J V V NC V NC V V DDQ DD DD DD DDQ K NC DQB V CK V NC DQA SS SS L DQB NC NC NC BA DQA NC M V DQB V CKE V NC V DDQ SS SS DDQ N DQB NC V A1 V DQA NC SS SS P NC DQPB V A0 V NC DQA SS SS R NC A LBO V FT ANC DD T NC A A NC A A ZZ U V TMS TDI TCK TDO NC V DDQ DDQ Rev: 1.01 8/2011 2/29 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see