GS864018/32/36T-300/250/200/167 300 MHz167 MHz 100-Pin TQFP 4M x 18, 2M x 32, 2M x 36 2.5 V or 3.3 V V Commercial Temp DD 72Mb Sync Burst SRAMs Industrial Temp 2.5 V or 3.3 V I/O cycles can be initiated with either ADSP or ADSC inputs. In Features Burst mode, subsequent burst addresses are generated FT pin for user-configurable flow through or pipeline internally and are controlled by ADV. The burst address operation counter may be configured to count in either linear or Single Cycle Deselect (SCD) operation interleave order with the Linear Burst Order (LBO) input. The 2.5 V or 3.3 V +10%/10% core power supply Burst function need not be used. New addresses can be loaded 2.5 V or 3.3 V I/O supply on every cycle with no degradation of chip performance. LBO pin for Linear or Interleaved Burst mode Internal input resistors on mode pins allow floating mode pins Flow Through/Pipeline Reads Default to Interleaved Pipeline mode The function of the Data Output register can be controlled by Byte Write (BW) and/or Global Write (GW) operation the user via the FT mode pin (Pin 14). Holding the FT mode Internal self-timed write cycle pin low places the RAM in Flow Through mode, causing Automatic power-down for portable applications output data to bypass the Data Output Register. Holding FT JEDEC-standard 100-lead TQFP package high places the RAM in Pipeline mode, activating the rising- RoHS-compliant 100-lead TQFP package available edge-triggered Data Output Register. Byte Write and Global Write Functional Description Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write Applications signals (Bx). In addition, Global Write (GW) is available for The GS864018/32/36T is a 75,497,472-bit high performance writing all bytes at one time, regardless of the Byte Write synchronous SRAM with a 2-bit burst address counter. control inputs. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device Sleep Mode now finds application in synchronous SRAM applications, Low power (Sleep mode) is attained through the assertion ranging from DSP main store to networking chip set support. (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst Core and Interface Voltages control inputs (ADSP, ADSC, ADV), and write control inputs The GS864018/32/36T operates on a 2.5 V or 3.3 V power (Bx, BW, GW) are synchronous and are controlled by a supply. All input are 3.3 V and 2.5 V compatible. Separate positive-edge-triggered clock input (CK). Output enable (G) output power (V ) pins are used to decouple output noise DDQ and power down control (ZZ) are asynchronous inputs. Burst from the internal circuits and are 3.3 V and 2.5 V compatible. Parameter Synopsis -300 -250 -200 -167 Unit t 2.3 2.5 3.0 3.4 ns KQ 3.3 4.0 5.0 6.0 ns Pipeline tCycle 3-1-1-1 Curr (x18) 400 340 290 260 mA Curr (x32/x36) 480 410 350 305 mA t 5.5 6.5 7.5 8.0 ns KQ Flow 5.5 6.5 7.5 8.0 ns tCycle Through Curr (x18) 285 245 220 210 mA 2-1-1-1 Curr (x32/x36) 330 280 250 240 mA Rev: 1.03a 2/2009 1/24 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS864018/32/36T-300/250/200/167 GS864018 100-Pin TQFP Pinout (Package T) 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 4M x 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 67 FT SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 DQA DQB 23 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either V or V . These pins can also be left floating. DD SS Rev: 1.03a 2/2009 2/24 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see