GS864218/36B-250M GS864272C-250M 250 MHz 4M x 18, 2M x 36, 1M x 72 119- & 209-Pin BGA 2.5 V or 3.3 V V DD Military Temp 72Mb S/DCD Sync Burst SRAMs 2.5 V or 3.3 V I/O either linear or interleave order with the Linear Burst Order (LBO) Features input. The Burst function need not be used. New addresses can be Military Temperature Range FT pin for user-configurable flow through or pipeline operation loaded on every cycle with no degradation of chip performance. Single/Dual Cycle Deselect selectable Flow Through/Pipeline Reads IEEE 1149.1 JTAG-compatible Boundary Scan The function of the Data Output register can be controlled by the ZQ mode pin for user-selectable high/low output drive user via the FT mode . Holding the FT mode pin low places the 2.5 V +10%/10% core power supply RAM in Flow Through mode, causing output data to bypass the 3.3 V +10%/10% core power supply Data Output Register. Holding FT high places the RAM in 2.5 V or 3.3 V I/O supply Pipeline mode, activating the rising-edge-triggered Data Output LBO pin for Linear or Interleaved Burst mode Register. Internal input resistors on mode pins allow floating mode pins SCD and DCD Pipelined Reads Default to SCD x18/x36 Interleaved Pipeline mode The GS864218B/36B/72C-250M is a SCD (Single Cycle Byte Write (BW) and/or Global Write (GW) operation Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous Internal self-timed write cycle SRAM. DCD SRAMs pipeline disable commands to the same Automatic power-down for portable applications degree as read commands. SCD SRAMs pipeline deselect JEDEC-standard 119- and 209-bump BGA package commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command Functional Description has been captured in the input registers. DCD RAMs hold the Applications deselect command for one full cycle and then begin turning off The GS864218B/36B/72C-250M is a 75,497,472-bit high their outputs just after the second rising edge of clock. The user performance synchronous SRAM with a 2-bit burst address may configure this SRAM for either mode of operation using the counter. Although of a type originally developed for Level 2 SCD mode input. Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging Byte Write and Global Write from DSP main store to networking chip set support. Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write Controls signals (Bx). In addition, Global Write (GW) is available for Addresses, data I/Os, chip enable (E1), address burst control writing all bytes at one time, regardless of the Byte Write control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, inputs. GW) are synchronous and are controlled by a positive-edge- triggered clock input (CK). Output enable (G) and power down FLXDrive control (ZZ) are asynchronous inputs. Burst cycles can be initiated The ZQ pin allows selection between high drive strength (ZQ low) with either ADSP or ADSC inputs. In Burst mode, subsequent for multi-drop bus applications and normal drive strength (ZQ burst addresses are generated internally and are controlled by floating or high) point-to-point applications. See the Output Driver ADV. The burst address counter may be configured to count in Characteristics chart for details. Parameter Synopsis -250M Unit t (x18/x36) 2.5 ns KQ 3.0 ns t (x72) KQ 4.0 ns Pipeline tCycle 3-1-1-1 Curr (x18) 565 mA Curr (x36) 490 mA Curr (x72) 385 mA t 6.5 ns KQ tCycle 6.5 ns Flow Through Curr (x18) 410 mA 2-1-1-1 Curr (x36) 330 mA Curr (x72) 290 mA Rev: 1.00 1/2011 1/35 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS864218/36B-250M GS864272C-250M 209-Bump BGAx72 Common I/OTop View (Package C) 1 2 3 4 5 6 7 8 9 10 11 A DQG DQG A E2 ADSP ADSC ADV E3 A DQB DQB A B DQG DQG BC BG NC BW A BB BF DQB DQB B C DQG DQG BH BD NC E1 NC BE BA DQB DQB C V V D DQG DQG NC NC G GW NC DQB DQB D SS SS V V V V V V V E DQPG DQPC DQPF DQPB E DDQ DDQ DD DD DD DDQ DDQ V V V V V V F DQC DQC ZQ DQF DQF F SS SS SS SS SS SS V V V V V V G DQC DQC MCH DQF DQF G DDQ DDQ DD DD DDQ DDQ V V V V V H DQC DQC MCL V DQF DQF H SS SS SS SS SS SS V V V V V V J DQC DQC MCL DQF DQF J DDQ DDQ DD DD DDQ DDQ V V K NC NC CK NC MCL NC NC NC NC K SS SS V V V V V V L DQH DQH FT DQA DQA L DDQ DDQ DD DD DDQ DDQ V V V V V V M DQH DQH MCL DQA DQA M SS SS SS SS SS SS V V V V V V N DQH DQH SCD DQA DQA N DDQ DDQ DD DD DDQ DDQ V V V V V V P DQH DQH ZZ DQA DQA P SS SS SS SS SS SS V V V V V V V R DQPD DQPH DQPA DQPE R DDQ DDQ DD DD DD DDQ DDQ V V T DQD DQD NC NC LBO NC NC DQE DQE T SS SS U DQD DQD A A A A A A A DQE DQE U V DQD DQD A A A A1 A A A DQE DQE V W DQD DQD TMS TDI A A0 A TDO TCK DQE DQE W 2 11 x 19 Bump BGA14 x 22 mm Body1 mm Bump Pitch Rev: 1.00 1/2011 2/35 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see