GS864218(B)/GS864236(B)/GS864272(C) 119- & 209-Pin BGA 300 MHz167 MHz 4M x 18, 2M x 36, 1M x 72 Commercial Temp 2.5 V or 3.3 V V DD 72Mb S/DCD Sync Burst SRAMs Industrial Temp 2.5 V or 3.3 V I/O either linear or interleave order with the Linear Burst Order (LBO) Features input. The Burst function need not be used. New addresses can be FT pin for user-configurable flow through or pipeline operation Single/Dual Cycle Deselect selectable loaded on every cycle with no degradation of chip performance. IEEE 1149.1 JTAG-compatible Boundary Scan Flow Through/Pipeline Reads ZQ mode pin for user-selectable high/low output drive The function of the Data Output register can be controlled by the 2.5 V +10%/10% core power supply user via the FT mode . Holding the FT mode pin low places the 3.3 V +10%/10% core power supply RAM in Flow Through mode, causing output data to bypass the 2.5 V or 3.3 V I/O supply Data Output Register. Holding FT high places the RAM in LBO pin for Linear or Interleaved Burst mode Pipeline mode, activating the rising-edge-triggered Data Output Internal input resistors on mode pins allow floating mode pins Register. Default to SCD x18/x36 Interleaved Pipeline mode SCD and DCD Pipelined Reads Byte Write (BW) and/or Global Write (GW) operation The GS864218/36/72 is a SCD (Single Cycle Deselect) and DCD Internal self-timed write cycle (Dual Cycle Deselect) pipelined synchronous SRAM. DCD Automatic power-down for portable applications SRAMs pipeline disable commands to the same degree as read JEDEC-standard 119- and 209-bump BGA package commands. SCD SRAMs pipeline deselect commands one stage RoHS-compliant 119- and 209-bump BGA packages available less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been Functional Description captured in the input registers. DCD RAMs hold the deselect Applications command for one full cycle and then begin turning off their The GS864218/36/72 is a 75,497,472-bit high performance outputs just after the second rising edge of clock. The user may synchronous SRAM with a 2-bit burst address counter. Although configure this SRAM for either mode of operation using the SCD of a type originally developed for Level 2 Cache applications mode input. supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from Byte Write and Global Write DSP main store to networking chip set support. Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write Controls signals (Bx). In addition, Global Write (GW) is available for Addresses, data I/Os, chip enable (E1), address burst control writing all bytes at one time, regardless of the Byte Write control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, inputs. GW) are synchronous and are controlled by a positive-edge- triggered clock input (CK). Output enable (G) and power down FLXDrive control (ZZ) are asynchronous inputs. Burst cycles can be initiated The ZQ pin allows selection between high drive strength (ZQ low) with either ADSP or ADSC inputs. In Burst mode, subsequent for multi-drop bus applications and normal drive strength (ZQ burst addresses are generated internally and are controlled by floating or high) point-to-point applications. See the Output Driver ADV. The burst address counter may be configured to count in Characteristics chart for details. Parameter Synopsis -300 -250 -200 -167 Unit t (x18/x36) 2.3 2.5 3.0 3.4 ns KQ 3.0 3.0 3.0 3.4 ns t (x72) KQ 3.3 4.0 5.0 6.0 ns Pipeline tCycle 3-1-1-1 Curr (x18) 400 340 290 260 mA Curr (x36) 480 410 350 305 mA Curr (x72) 590 520 435 380 mA t 5.5 6.5 7.5 8.0 ns KQ tCycle 5.5 6.5 7.5 8.0 ns Flow Through Curr (x18) 285 245 220 210 mA 2-1-1-1 Curr (x36) 330 280 250 240 mA Curr (x72) 425 370 315 300 mA Rev: 1.04a 2/2009 1/36 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS864218(B)/GS864236(B)/GS864272(C) 209-Bump BGAx72 Common I/OTop View (Package C) 1 2 3 4 5 6 7 8 9 10 11 A DQG DQG A E2 ADSP ADSC ADV E3 A DQB DQB A B DQG DQG BC BG NC BW A BB BF DQB DQB B C DQG DQG BH BD NC E1 NC BE BA DQB DQB C V V D DQG DQG NC NC G GW NC DQB DQB D SS SS V V V V V V V E DQPG DQPC DQPF DQPB E DDQ DDQ DD DD DD DDQ DDQ V V V V V V F DQC DQC ZQ DQF DQF F SS SS SS SS SS SS V V V V V V G DQC DQC MCH DQF DQF G DDQ DDQ DD DD DDQ DDQ V V V V V V H DQC DQC MCL DQF DQF H SS SS SS SS SS SS V V V V V V J DQC DQC MCL DQF DQF J DDQ DDQ DD DD DDQ DDQ V V K NC NC CK NC MCL NC NC NC NC K SS SS V V V V V V L DQH DQH FT DQA DQA L DDQ DDQ DD DD DDQ DDQ V V V V V V M DQH DQH MCL DQA DQA M SS SS SS SS SS SS V V V V V V N DQH DQH SCD DQA DQA N DDQ DDQ DD DD DDQ DDQ V V V V V V P DQH DQH ZZ DQA DQA P SS SS SS SS SS SS V V V V V V V R DQPD DQPH DQPA DQPE R DDQ DDQ DD DD DD DDQ DDQ V V T DQD DQD NC NC LBO NC NC DQE DQE T SS SS U DQD DQD A A A A A A A DQE DQE U V DQD DQD A A A A1 A A A DQE DQE V W DQD DQD TMS TDI A A0 A TDO TCK DQE DQE W 2 11 x 19 Bump BGA14 x 22 mm Body1 mm Bump Pitch Rev: 1.04a 2/2009 2/36 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see