GS8642Z36GB-167IV GSI Technology

GS8642Z18/36/72(B/C)-xxxV 119- & 209-Bump BGA 250 MHz167 MHz 72Mb Pipelined and Flow Through Commercial Temp 1.8 V or 2.5 V V DD Synchronous NBT SRAM Industrial Temp 1.8 V or 2.5 V I/O Features Because it is a synchronous device, address, data inputs, and NBT (No Bus Turn Around) functionality allows zero wait read/write control inputs are captured on the rising edge of the Read-Write-Read bus utilization fully pin-compatible with input clock. Burst order control (LBO) must be tied to a power both pipelined and flow through NtRAM, NoBL and rail for proper operation. Asynchronous inputs include the ZBT SRAMs Sleep mode enable (ZZ) and Output Enable. Output Enable can 1.8 V 2.5 V core power supply be used to override the synchronous control of the output 1.8 V or 2.5 V I/O supply drivers and turn the RAM s output drivers off at any time. User-configurable Pipeline and Flow Through mode Write cycles are internally self-timed and initiated by the rising ZQ mode pin for user-selectable high/low output drive edge of the clock input. This feature eliminates complex off- IEEE 1149.1 JTAG-compatible Boundary Scan chip write pulse generation required by asynchronous SRAMs LBO pin for Linear or Interleave Burst mode and simplifies input signal timing. Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices Byte write operation (9-bit Bytes) The GS8642Z18/36/72(B/C)-xxxV may be configured by the 3 chip enable signals for easy depth expansion user to operate in Pipeline or Flow Through mode. Operating ZZ Pin for automatic power-down as a pipelined synchronous device, in addition to the rising- JEDEC-standard 119- or 209-bump BGA package edge-triggered registers that capture input signals, the device RoHS-compliant 119- and 209-bump BGA packages incorporates a rising edge triggered output register. For read available cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and Functional Description then released to the output drivers at the next rising edge of The GS8642Z18/36/72(B/C)-xxxV is a 72Mbit Synchronous clock. Static SRAM. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL The GS8642Z18/36/72(B/C)-xxxV is implemented with GSI s or other pipelined read/double late write or flow through read/ high performance CMOS technology and is available in a single late write SRAMs, allow utilization of all available bus JEDEC-standard 119-bump or 209-bump BGA package. bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Parameter Synopsis -250 -200 -167 Unit t 3.0 3.0 3.4 ns KQ 4.0 5.0 6.0 ns tCycle Pipeline Curr (x18) 340 290 260 mA 3-1-1-1 Curr (x36) 410 350 305 mA Curr (x72) 520 435 380 mA t 6.5 7.5 8.0 ns KQ 6.5 7.5 8.0 ns tCycle Flow Through Curr (x18) 245 220 210 mA 2-1-1-1 Curr (x36) 280 250 240 mA Curr (x72) 370 315 300 mA Rev: 1.04a 2/2009 1/33 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8642Z18/36/72(B/C)-xxxV GS8642Z72C-xxxV Pad Out209-Bump BGATop View (Package C) 1 2 3 4 5 6 7 8 9 10 11 A DQG DQG A E2 A ADV A E3 A DQB DQB A B DQG DQG BC BG NC W A BB BF DQB DQB B C DQG DQG BH BD NC E1 NC BE BA DQB DQB C D DQG DQG V NC NC G NC NC V DQB DQB D SS SS E DQPG DQPC V V V V V V V DQPF DQPB E DDQ DDQ DD DD DD DDQ DDQ F DQC DQC V V V ZQ V V V DQF DQF F SS SS SS SS SS SS G DQC DQC V V V MCH V V V DQF DQF G DDQ DDQ DD DD DDQ DDQ H DQC DQC V V V MCL V V V DQF DQF H SS SS SS SS SS SS J DQC DQC V V V MCH V V V DQF DQF J DDQ DDQ DD DD DDQ DDQ K NC NC CK NC V CKE V NC NC NC NC K SS SS L DQH DQH V V V FT V V V DQA DQA L DDQ DDQ DD DD DDQ DDQ M DQH DQH V V V MCL V V V DQA DQA M SS SS SS SS SS SS N DQH DQH V V V MCH V V V DQA DQA N DDQ DDQ DD DD DDQ DDQ P DQH DQH V V V ZZ V V V DQA DQA P SS SS SS SS SS SS R DQPD DQPH V V V V V V V DQPA DQPE R DDQ DDQ DD DD DD DDQ DDQ T DQD DQD V NC NC LBO NC NC V DQE DQE T SS SS U DQD DQD NC A A A A A NC DQE DQE U V DQD DQD A A A A1 A A A DQE DQE V W DQD DQD TMS TDI A A0 A TDO TCK DQE DQE W 2 11 x 19 Bump BGA14 x 22 mm Body1 mm Bump Pitch Rev: 1.04a 2/2009 2/33 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see