GS864418/36E-250/225/200/166/150/133
250 MHz133MHz
165-Bump BGA
4M x 18, 2M x 36
2.5 V or 3.3 V V
Commercial Temp
DD
72Mb S/DCD Sync Burst SRAMs
Industrial Temp
2.5 V or 3.3 V I/O
Flow Through/Pipeline Reads
Features
The function of the Data Output register can be controlled by the user
FT pin for user-configurable flow through or pipeline operation
via the FT mode . Holding the FT mode pin low places the RAM in
Single/Dual Cycle Deselect selectable
Flow Through mode, causing output data to bypass the Data Output
IEEE 1149.1 JTAG-compatible Boundary Scan
Register. Holding FT high places the RAM in Pipeline mode,
ZQ mode pin for user-selectable high/low output drive
activating the rising-edge-triggered Data Output Register.
2.5 V or 3.3 V +10%/10% core power supply
2.5 V or 3.3 V I/O supply
SCD and DCD Pipelined Reads
The GS864418/36E is a SCD (Single Cycle Deselect) and DCD (Dual
LBO pin for Linear or Interleaved Burst mode
Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs
Internal input resistors on mode pins allow floating mode pins
pipeline disable commands to the same degree as read commands.
Default to SCD x18/x36 Interleaved Pipeline mode
SCD SRAMs pipeline deselect commands one stage less than read
Byte Write (BW) and/or Global Write (GW) operation
commands. SCD RAMs begin turning off their outputs immediately
Internal self-timed write cycle
after the deselect command has been captured in the input registers.
Automatic power-down for portable applications
DCD RAMs hold the deselect command for one full cycle and then
JEDEC-standard 165-bump BGA package
begin turning off their outputs just after the second rising edge of
RoHS-compliant 165-bump BGA package available
clock. The user may configure this SRAM for either mode of
Functional Description
operation using the SCD mode input.
Applications
Byte Write and Global Write
The GS864418/36E is a 75,497,472-bit high performance
Byte write operation is performed by using Byte Write enable (BW)
synchronous SRAM with a 2-bit burst address counter. Although of a
input combined with one or more individual byte write signals (Bx).
type originally developed for Level 2 Cache applications supporting
In addition, Global Write (GW) is available for writing all bytes at one
high performance CPUs, the device now finds application in
time, regardless of the Byte Write control inputs.
synchronous SRAM applications, ranging from DSP main store to
FLXDrive
networking chip set support.
The ZQ pin allows selection between high drive strength (ZQ low) for
Controls multi-drop bus applications and normal drive strength (ZQ floating or
Addresses, data I/Os, chip enable (E1), address burst control inputs
high) point-to-point applications. See the Output Driver
(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are
Characteristics chart for details.
synchronous and are controlled by a positive-edge-triggered clock
Sleep Mode
input (CK). Output enable (G) and power down control (ZZ) are
Low power (Sleep mode) is attained through the assertion (High) of
asynchronous inputs. Burst cycles can be initiated with either ADSP
the ZZ signal, or by stopping the clock (CK). Memory data is retained
or ADSC inputs. In Burst mode, subsequent burst addresses are
during Sleep mode.
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
Core and Interface Voltages
The GS864418/36E operates on a 2.5 V or 3.3 V power supply. All
with the Linear Burst Order (LBO) input. The Burst function need not
input are 3.3 V and 2.5 V compatible. Separate output power (V )
be used. New addresses can be loaded on every cycle with no
DDQ
degradation of chip performance.
pins are used to decouple output noise from the internal circuits and
are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
(x18/x36) 2.5 2.7 3.0 3.5 3.8 4.0 ns
t
KQ
4.0 4.4 5.0 6.0 6.7 7.5 ns
Pipeline tCycle
3-1-1-1
Curr (x18) 385 360 335 305 295 265 mA
Curr (x36) 450 415 385 345 325 295 mA
t
6.5 6.5 6.5 7.0 7.5 8.5 ns
KQ
Flow
tCycle 6.5 6.5 6.5 7.0 7.5 8.5 ns
Through
Curr (x18) 265 265 265 255 240 225 mA
2-1-1-1
Curr (x36) 290 290 290 280 265 245 mA
Rev: 1.07 2/2011 1/33 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see GS864418/36E-250/225/200/166/150/133
165-Bump BGAx18 Commom I/OTop View (Package E)
1 2 3 4 5 6 7 8 9 10 11
A NC A E1 BB NC E3 BW ADSC ADV A A A
B NC A E2 NC BA CK GW G ADSP A NC B
C NC NC V V V V V V V NC DQPA C
DDQ SS SS SS SS SS DDQ
D NC DQB V V V V V V V NC DQA D
DDQ DD SS SS SS DD DDQ
E NC DQB V V V V V V V NC DQA E
DDQ DD SS SS SS DD DDQ
F NC DQB V V V V V V V NC DQA F
DDQ DD SS SS SS DD DDQ
G NC DQB V V V V V V V NC DQA G
DDQ DD SS SS SS DD DDQ
H FT MCL NC V V V V V NC ZQ ZZ H
DD SS SS SS DD
J DQB NC V V V V V V V DQA NC J
DDQ DD SS SS SS DD DDQ
K DQB NC V V V V V V V DQA NC K
DDQ DD SS SS SS DD DDQ
L DQB NC V V V V V V V DQA NC L
DDQ DD SS SS SS DD DDQ
M DQB NC V V V V V V V DQA NC M
DDQ DD SS SS SS DD DDQ
N DQPB SCD V V NC A NC V V NC NC N
DDQ SS SS DDQ
P NC A A A TDI A1 TDO A A A A P
R LBO A A A TMS A0 TCK A A A A R
11 x 15 Bump BGA15 mm x 17 mm Body1.0 mm Bump Pitch
Rev: 1.07 2/2011 2/33 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see