GS8644Z18E/GS8644Z36E
250 MHz133MHz
165-Pin BGA
72Mb Pipelined and Flow Through
2.5 V or 3.3 V V
Commercial Temp
DD
Synchronous NBT SRAM
Industrial Temp
2.5 V or 3.3 V I/O
Features
Because it is a synchronous device, address, data inputs, and
NBT (No Bus Turn Around) functionality allows zero wait
read/write control inputs are captured on the rising edge of the
Read-Write-Read bus utilization; fully pin-compatible with
input clock. Burst order control (LBO) must be tied to a power
both pipelined and flow through NtRAM, NoBL and
rail for proper operation. Asynchronous inputs include the
ZBT SRAMs
Sleep mode enable (ZZ) and Output Enable. Output Enable can
2.5 V or 3.3 V +10%/10% core power supply
be used to override the synchronous control of the output
2.5 V or 3.3 V I/O supply
drivers and turn the RAM's output drivers off at any time.
User-configurable Pipeline and Flow Through mode
Write cycles are internally self-timed and initiated by the rising
ZQ mode pin for user-selectable high/low output drive
edge of the clock input. This feature eliminates complex off-
IEEE 1149.1 JTAG-compatible Boundary Scan
chip write pulse generation required by asynchronous SRAMs
LBO pin for Linear or Interleave Burst mode
and simplifies input signal timing.
Pin-compatible with 9Mb, 18Mb, and 36Mb devices
The GS8644Z18/36 may be configured by the user to operate
Byte write operation (9-bit Bytes)
in Pipeline or Flow Through mode. Operating as a pipelined
3 chip enable signals for easy depth expansion
synchronous device, in addition to the rising-edge-triggered
ZZ Pin for automatic power-down
registers that capture input signals, the device incorporates a
JEDEC-standard 165-BGA package
rising edge triggered output register. For read cycles, pipelined
RoHS-compliant 165-bump BGA package available
SRAM output data is temporarily stored by the edge-triggered
output register during the access cycle and then released to the
Functional Description
output drivers at the next rising edge of clock.
The GS8644Z18/36 is a 72Mbit Synchronous Static SRAM.
The GS8644Z18/36 is implemented with GSI's high
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
performance CMOS technology and is available in a JEDEC-
pipelined read/double late write or flow through read/single
standard 165-bump BGA package.
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
t (x18/x36) 2.5 2.7 3.0 3.5 3.8 4.0 ns
KQ
3.0 3.0 3.0 3.5 3.8 4.0 ns
t (x72)
KQ
4.0 4.4 5.0 6.0 6.7 7.5 ns
Pipeline
tCycle
3-1-1-1
Curr (x18) 385 360 335 305 295 265 mA
Curr (x36) 450 415 385 345 325 295 mA
Curr (x72) 540 505 460 405 385 345 mA
t
6.5 6.5 6.5 7.0 7.5 8.5 ns
KQ
6.5 6.5 6.5 7.0 7.5 8.5 ns
Flow tCycle
Through
Curr (x18) 265 265 265 255 240 225 mA
2-1-1-1
Curr (x36) 290 290 290 280 265 245 mA
Curr (x72) 345 345 345 335 315 300 mA
Rev: 1.05b 5/2010 1/31 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see GS8644Z18E/GS8644Z36E
165 Bump BGAx18 Common I/OTop View (Package E)
1 2 3 4 5 6 7 8 9 10 11
A NC A E1 BB NC E3 CKE ADV A A A A
B NC A E2 NC BA CK W G A A NC B
C NC NC V V V V V V V NC DQPA C
DDQ SS SS SS SS SS DDQ
D NC DQB V V V V V V V NC DQA D
DDQ DD SS SS SS DD DDQ
E NC DQB V V V V V V V NC DQA E
DDQ DD SS SS SS DD DDQ
F NC DQB V V V V V V V NC DQA F
DDQ DD SS SS SS DD DDQ
G NC DQB V V V V V V V NC DQA G
DDQ DD SS SS SS DD DDQ
H FT MCH NC V V V V V NC ZQ ZZ H
DD SS SS SS DD
J DQB NC V V V V V V V DQA NC J
DDQ DD SS SS SS DD DDQ
K DQB NC V V V V V V V DQA NC K
DDQ DD SS SS SS DD DDQ
L DQB NC V V V V V V V DQA NC L
DDQ DD SS SS SS DD DDQ
M DQB NC V V V V V V V DQA NC M
DDQ DD SS SS SS DD DDQ
N DQPB NC V V NC NC NC V V NC NC N
DDQ SS SS DDQ
P NC A A A TDI A1 TDO A A A NC P
R LBO A A A TMS A0 TCK A A A A R
11 x 15 Bump BGA15 mm x 17 mm Body1.0 mm Bump Pitch
Rev: 1.05b 5/2010 2/31 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see