GS8662DT20/38BD-550/500/450/400/350 GS8662DT06/11BD-500/450/400/350 550 MHz350 MHz 165-Bump BGA TM 72Mb SigmaQuad-II+ 1.8 V V DD Commercial Temp 1.8 V or 1.5 V I/O Burst of 4 SRAM Industrial Temp SRAMs. The GS8662DT06/11/20/38BD SigmaQuad SRAMs Features are just one element in a family of low power, low voltage 2.5 Clock Latency HSTL I/O SRAMs designed to operate at the speeds needed to Simultaneous Read and Write SigmaQuad Interface implement economical high performance networking systems. JEDEC-standard pinout and package Dual Double Data Rate interface Byte Write controls sampled at data-in time Clocking and Addressing Schemes Burst of 4 Read and Write Dual-Range On-Die Termination (ODT) on Data (D), Byte The GS8662DT06/11/20/38BD SigmaQuad-II+ SRAMs are Write (BW), and Clock (K, K) intputs synchronous devices. They employ two input register clock 1.8 V +100/100 mV core power supply inputs, K and K. K and K are independent single-ended clock 1.5 V or 1.8 V HSTL Interface inputs, not differential inputs to a single differential clock input Pipelined read operation buffer. Fully coherent read and write pipelines ZQ pin for programmable output drive strength Each internal read and write operation in a SigmaQuad-II+ B4 Data Valid Pin (QVLD) Support RAM is four times wider than the device I/O bus. An input IEEE 1149.1 JTAG-compliant Boundary Scan data bus de-multiplexer is used to accumulate incoming data 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package before it is simultaneously written to the memory array. An RoHS-compliant 165-bump BGA package available output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore the address SigmaQuad-II Family Overview field of a SigmaQuad-II+ B4 RAM is always two address pins The GS8662DT06/11/20/38BD are built in compliance with less than the advertised index depth (e.g., the 8M x 8 has a 2M the SigmaQuad-II+ SRAM pinout standard for Separate I/O addressable index). synchronous SRAMs. They are 75,497,472-bit (72Mb) Parameter Synopsis (x18/x36) -550 -500 -450 -400 -350 tKHKH 1.81 ns 2.0 ns 2.2 ns 2.5 ns 2.86 ns tKHQV 0.29ns 0.33 ns 0.37 ns 0.45 ns 0.45 ns Parameter Synopsis (x8/x9) -500 -450 -400 -350 tKHKH 2.0 ns 2.2 ns 2.5 ns 2.86 ns tKHQV 0.33 ns 0.37ns 0.45 ns 0.45 ns Rev: 1.00b 8/2017 1/33 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8662DT20/38BD-550/500/450/400/350 GS8662DT06/11BD-500/450/400/350 2M x 36 SigmaQuad-II+ SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 NC/SA NC/SA A CQ SA W BW2 K BW1 R SA CQ (288Mb) (144Mb) B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8 C D27 Q28 D19 V SA NC SA V D16 Q7 D8 SS SS D D28 D20 Q19 V V V V V Q16 D15 D7 SS SS SS SS SS E Q29 D29 Q20 V V V V V Q15 D6 Q6 DDQ SS SS SS DDQ F Q30 Q21 D21 V V V V V D14 Q14 Q5 DDQ DD SS DD DDQ G D30 D22 Q22 V V V V V Q13 D13 D5 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J D31 Q31 D23 V V V V V D12 Q4 D4 DDQ DD SS DD DDQ K Q32 D32 Q23 V V V V V Q12 D3 Q3 DDQ DD SS DD DDQ L Q33 Q24 D24 V V V V V D11 Q11 Q2 DDQ SS SS SS DDQ M D33 Q34 D25 V V V V V D10 Q1 D2 SS SS SS SS SS N D34 D26 Q25 V SA SA SA V Q10 D9 D1 SS SS P Q35 D35 Q26 SA SA QVLD SA SA Q9 D0 Q0 R TDO TCK SA SA SA ODT SA SA SA TMS TDI 11 x 15 Bump BGA13 x 15 mm Body1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8 BW1 controls writes to D9:D17 BW2 controls writes to D18:D26 BW3 controls writes to D27:D35 2. Pins A2 and A10 are the expansion addresses. Rev: 1.00b 8/2017 2/33 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see