GS8662R36BGD-300I GSI Technology

GS8662R08/09/18/36BD-400/350/333/300/250 400 MHz250 MHz 165-Bump BGA TM 72Mb SigmaDDR-II 1.8 V V Commercial Temp DD Industrial Temp Burst of 4 SRAM 1.8 V and 1.5 V I/O inputs, not differential inputs to a single differential clock input Features buffer. The device also allows the user to manipulate the Simultaneous Read and Write SigmaDDR Interface output register clock inputs quasi independently with the C and Common I/O bus C clock inputs. C and C are also independent single-ended JEDEC-standard pinout and package clock inputs, not differential inputs. If the C clocks are tied Double Data Rate interface high, the K clocks are routed internally to fire the output Byte Write (x36, x18 and x9) and Nybble Write (x8) function registers instead. Burst of 4 Read and Write 1.8 V +100/100 mV core power supply Each internal read and write operation in a SigmaDDR-II B4 1.5 V or 1.8 V HSTL Interface RAM is four times wider than the device I/O bus. An input Pipelined read operation with self-timed Late Write data bus de-multiplexer is used to accumulate incoming data Fully coherent read and write pipelines before it is simultaneously written to the memory array. An ZQ pin for programmable output drive strength output data multiplexer is used to capture the data produced IEEE 1149.1 JTAG-compliant Boundary Scan from a single memory array read and then route it to the Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb appropriate output drivers as needed. devices 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package When a new address is loaded into a x18 or x36 version of the RoHS-compliant 165-bump BGA package available part, A0 and A1 are used to initialize the pointers that control the data multiplexer / de-multiplexer so the RAM can perform SigmaDDR Family Overviewcritical word firs operations. From an external address point The GS8662R08/09/18/36BD are built in compliance with the of view, regardless of the starting point, the data transfers SigmaDDR-II SRAM pinout standard for Common I/O always follow the same linear sequence 00, 01, 10, 11 or synchronous SRAMs. They are 75,497,472-bit (72Mb) 01, 10, 11, 00 or 10, 11, 00, 01 or 11, 00, 01, 10 (where SRAMs. The GS8662R08/09/18/36BD SigmaDDR-II SRAMs the digits shown represent A1, A0). are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to Unlike the x18 and x36 versions, the input and output data implement economical high performance networking systems. multiplexers of the x8 and x9 versions are not preset by address inputs and therefore do not allowcritical word firs Clocking and Addressing Schemes operations. The address fields of the x8 and x9 SigmaDDR-II B4 RAMs are two address pins less than the advertised index The GS8662R08/09/18/36BD SigmaDDR-II SRAMs are depth (e.g., the 8M x 8 has a 2M addressable index, and A0 and synchronous devices. They employ two input register clock A1 are not accessible address pins). inputs, K and K. K and K are independent single-ended clock Parameter Synopsis -400 -350 -333 -300 -250 tKHKH 2.5 ns 2.86 ns 3.0 ns 3.3 ns 4.0 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns Rev: 1.02d 8/2017 1/35 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8662R08/09/18/36BD-400/350/333/300/250 2M x 36 SigmaDDR-II SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 NC/SA A CQ SA R/W BW2 K BW1 LD SA SA CQ (144Mb) NC/SA B NC DQ27 DQ18 SA BW3 K BW0 SA NC DQ8 (288Mb) C NC NC DQ28 V SA SA0 SA1 V NC DQ17 DQ7 SS SS D NC DQ29 DQ19 V V V V V NC NC DQ16 SS SS SS SS SS E NC NC DQ20 V V V V V NC DQ15 DQ6 DDQ SS SS SS DDQ F NC DQ30 DQ21 V V V V V NC NC DQ5 DDQ DD SS DD DDQ G NC DQ31 DQ22 V V V V V NC NC DQ14 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC DQ32 V V V V V NC DQ13 DQ4 DDQ DD SS DD DDQ K NC NC DQ23 V V V V V NC DQ12 DQ3 DDQ DD SS DD DDQ L NC DQ33 DQ24 V V V V V NC NC DQ2 DDQ SS SS SS DDQ M NC NC DQ34 V V V V V NC DQ11 DQ1 SS SS SS SS SS N NC DQ35 DQ25 V SA SA SA V NC NC DQ10 SS SS P NC NC DQ26 SA SA C SA SA NC DQ9 DQ0 R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA13 x 15 mm Body1 mm Bump Pitch Notes: 1. BW0 controls writes to DQ0:DQ8 BW1 controls writes to DQ9:DQ17 BW2 controls writes to DQ18:DQ26 BW3 controls writes to DQ27:DQ35. 2. A2 and B9 are the expansion addresses. Rev: 1.02d 8/2017 2/35 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see