GS88018/32/36CT-xxxI 333 MHz150 MHz 512K x 18, 256K x 32, 256K x 36 100-Pin TQFP 2.5 V or 3.3 V V DD Industrial Temp 9Mb Sync Burst SRAMs 2.5 V or 3.3 V I/O interleave order with the Linear Burst Order (LBO) input. The Features Burst function need not be used. New addresses can be loaded FT pin for user-configurable flow through or pipeline on every cycle with no degradation of chip performance. operation Single Cycle Deselect (SCD) operation Flow Through/Pipeline Reads 2.5 V or 3.3 V +10%/10% core power supply The function of the Data Output register can be controlled by 2.5 V or 3.3 V I/O supply the user via the FT mode pin (Pin 14). Holding the FT mode LBO pin for Linear or Interleaved Burst mode pin low places the RAM in Flow Through mode, causing Internal input resistors on mode pins allow floating mode pins output data to bypass the Data Output Register. Holding FT Default to Interleaved Pipeline mode high places the RAM in Pipeline mode, activating the rising- Byte Write (BW) and/or Global Write (GW) operation edge-triggered Data Output Register. Internal self-timed write cycle SCD Pipelined Reads Automatic power-down for portable applications The GS88018/32/36CT is a SCD (Single Cycle Deselect) JEDEC-standard 100-lead TQFP package pipelined synchronous SRAM. DCD (Dual Cycle Deselect) RoHS-compliant 100-lead TQFP package available versions are also available. SCD SRAMs pipeline deselect Functional Description commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect Applications command has been captured in the input registers. The GS88018/32/36CT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a Byte Write and Global Write 2-bit burst address counter. Although of a type originally Byte write operation is performed by using Byte Write enable developed for Level 2 Cache applications supporting high (BW) input combined with one or more individual byte write performance CPUs, the device now finds application in signals (Bx). In addition, Global Write (GW) is available for synchronous SRAM applications, ranging from DSP main writing all bytes at one time, regardless of the Byte Write store to networking chip set support. control inputs. Controls Sleep Mode Addresses, data I/Os, chip enables (E1, E2, E3), address burst Low power (Sleep mode) is attained through the assertion control inputs (ADSP, ADSC, ADV), and write control inputs (High) of the ZZ signal, or by stopping the clock (CK). (Bx, BW, GW) are synchronous and are controlled by a Memory data is retained during Sleep mode. positive-edge-triggered clock input (CK). Output enable (G) Core and Interface Voltages and power down control (ZZ) are asynchronous inputs. Burst The GS88018/32/36CT operates on a 2.5 V or 3.3 V power cycles can be initiated with either ADSP or ADSC inputs. In supply. All input are 3.3 V and 2.5 V compatible. Separate Burst mode, subsequent burst addresses are generated output power (V ) pins are used to decouple output noise DDQ internally and are controlled by ADV. The burst address from the internal circuits and are 3.3 V and 2.5 V compatible. counter may be configured to count in either linear or Parameter Synopsis -333I -300I -250I -200I -150I Unit t 2.5 2.5 2.5 3.0 3.8 ns KQ 3.0 3.3 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 260 245 215 190 160 mA Curr (x32/x36) 300 280 245 215 180 mA t 4.5 5.0 5.5 6.5 7.5 ns KQ 4.5 5.0 5.5 6.5 7.5 ns Flow Through tCycle 2-1-1-1 Curr (x18) 200 185 180 160 148 mA Curr (x32/x36) 225 210 200 180 165 mA Rev: 1.04 6/2012 1/23 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS88018/32/36CT-xxxI GS88018C 100-Pin TQFP Pinout 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 512K x 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 67 FT SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB6 V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either V or V . These pins can also be left floating. DD SS Rev: 1.04 6/2012 2/23 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see