GS88037CT-xxxI 333 MHz200 MHz 256K x 36 100-Pin TQFP 2.5 V or 3.3 V V DD Industrial Temp 9Mb Sync Burst SRAM 2.5 V or 3.3 V I/O Burst mode, subsequent burst addresses are generated Features internally and are controlled by ADV. The burst address Single Cycle Deselect (SCD) operation counter may be configured to count in either linear or 2.5 V or 3.3 V +10%/10% core power supply interleave order with the Linear Burst Order (LBO) input. The 2.5 V or 3.3 V I/O supply Burst function need not be used. New addresses can be loaded LBO pin for Linear or Interleaved Burst mode on every cycle with no degradation of chip performance. Internal input resistors on mode pins allow floating mode pins Default to Interleaved Pipeline mode SCD Pipelined Reads Byte Write (BW) and/or Global Write (GW) operation The GS88037CT is a SCD (Single Cycle Deselect) pipelined Internal self-timed write cycle synchronous SRAM. DCD (Dual Cycle Deselect) versions are Automatic power-down for portable applications also available. SCD SRAMs pipeline deselect commands one JEDEC-standard 100-lead TQFP package stage less than read commands. SCD RAMs begin turning off Ro-HS-compliant 100-lead TQFP package available their outputs immediately after the deselect command has been captured in the input registers. Functional Description Byte Write and Global Write Byte write operation is performed by using Byte Write enable Applications (BW) input combined with one or more individual byte write The GS88037CT is a 9,437,184-bit (8,388,608-bit for x32 signals (Bx). In addition, Global Write (GW) is available for version) high performance synchronous SRAM with a writing all bytes at one time, regardless of the Byte Write 2-bit burst address counter. Although of a type originally control inputs. developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in Sleep Mode synchronous SRAM applications, ranging from DSP main Low power (Sleep mode) is attained through the assertion store to networking chip set support. (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst Core and Interface Voltages control inputs (ADSP, ADSC, ADV), and write control inputs The GS88037CT operates on a 2.5 V or 3.3 V power supply. (Bx, BW, GW) are synchronous and are controlled by a All input are 3.3 V and 2.5 V compatible. Separate output positive-edge-triggered clock input (CK). Output enable (G) power (V ) pins are used to decouple output noise from the DDQ and power down control (ZZ) are asynchronous inputs. Burst internal circuits and are 3.3 V and 2.5 V compatible. cycles can be initiated with either ADSP or ADSC inputs. In Parameter Synopsis -333I -300I -250I -200I Unit Pipeline t 2.0 2.2 2.3 2.7 ns KQ 3-1-1-1 3.0 3.3 4.0 5.0 ns tCycle Curr (x36) 300 280 245 215 mA Rev: 1.04 7/2012 1/19 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS88037CT-xxxI GS88037C 100-Pin TQFP Pinout 10099 989796959493929190898887868584838281 DQPB DQPC 1 80 DQB DQC 2 79 DQB DQC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS DQB DQC 6 75 DQB 7 DQC 74 DQB DQC 8 73 DQB DQC 9 72 256K x 36 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQB DQC 12 69 DQB 13 DQC 68 V 14 67 SS V /DNU DDQ NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQD 18 63 DQA 19 62 DQD V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQD 59 23 DQA DQD 58 DQA DQD 24 57 DQA 25 56 DQD V 26 55 V SS SS V 27 54 V DDQ DDQ DQA 28 53 DQD 29 52 DQA DQD 30 DQPA DQPD 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.04 7/2012 2/19 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see