GS880F18/32/36CT-xxxI 4.5 ns7.5 ns 512K x 18, 256K x 32, 256K x 36 100-Pin TQFP 2.5 V or 3.3 V V DD Industrial Temp 9Mb Sync Burst SRAMs 2.5 V or 3.3 V I/O interleave order with the Linear Burst Order (LBO) input. The Features Burst function need not be used. New addresses can be loaded Flow Through mode operation Pin 14 = No Connect on every cycle with no degradation of chip performance. 2.5 V or 3.3 V +10%/10% core power supply Designing For Compatibility 2.5 V or 3.3 V I/O supply The JEDEC standard for Burst RAMS calls for a FT mode pin LBO pin for Linear or Interleaved Burst mode option on Pin 14. Board sites for flow through Burst RAMS Internal input resistors on mode pins allow floating mode pins should be designed with V connected to the FT pin location Byte Write (BW) and/or Global Write (GW) operation SS Internal self-timed write cycle to ensure the broadest access to multiple vendor sources. Automatic power-down for portable applications Boards designed with FT pin pads tied low may be stuffed with JEDEC-standard 100-lead TQFP package GSIs pipeline/flow through-configurable Burst RAMs or any RoHS-compliant 100-lead TQFP package available vendors flow through or configurable Burst SRAM. Boards designed with the FT pin location tied high or floating must employ a non-configurable flow through Burst RAM, like this Functional Description RAM, to achieve flow through functionality. Applications Byte Write and Global Write The GS880F18/32/36CT is a 9,437,184-bit (8,388,608-bit for Byte write operation is performed by using Byte Write enable x32 version) high performance synchronous SRAM with a (BW) input combined with one or more individual byte write 2-bit burst address counter. Although of a type originally signals (Bx). In addition, Global Write (GW) is available for developed for Level 2 Cache applications supporting high writing all bytes at one time, regardless of the Byte Write performance CPUs, the device now finds application in control inputs. synchronous SRAM applications, ranging from DSP main store to networking chip set support. Sleep Mode Low power (Sleep mode) is attained through the assertion Controls (High) of the ZZ signal, or by stopping the clock (CK). Addresses, data I/Os, chip enables (E1, E2, E3), address burst Memory data is retained during Sleep mode. control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a Core and Interface Voltages positive-edge-triggered clock input (CK). Output enable (G) The GS880F18/32/36CT operates on a 2.5 V or 3.3 V power and power down control (ZZ) are asynchronous inputs. Burst supply. All input are 3.3 V and 2.5 V compatible. Separate cycles can be initiated with either ADSP or ADSC inputs. In output power (V ) pins are used to decouple output noise DDQ Burst mode, subsequent burst addresses are generated from the internal circuits and are 3.3 V and 2.5 V compatible. internally and are controlled by ADV. The burst address counter may be configured to count in either linear or Parameter Synopsis -4.5I -5I -5.5I -6.5I -7.5I Unit t 4.5 5.0 5.5 6.5 7.5 ns KQ 4.5 5.0 5.5 6.5 7.5 ns Flow Through tCycle 2-1-1-1 Curr (x18) 200 185 180 160 148 mA Curr (x32/x36) 225 210 200 180 165 mA Rev: 1.04 7/2012 1/23 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS880F18/32/36CT-xxxI GS880F18C 100-Pin TQFP Pinout (Package T) 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 512K x 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 67 NC SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either V or V . These pins can also be left floating. DD SS Rev: 1.04 7/2012 2/23 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see