GS880Z18/32/36CT-xxx 333 MHz150 MHz 9Mb Pipelined and Flow Through 100-Pin TQFP 2.5 V or 3.3 V V DD Commercial Temp Synchronous NBT SRAM 2.5 V or 3.3 V I/O rail for proper operation. Asynchronous inputs include the Features Sleep mode enable (ZZ) and Output Enable. Output Enable can NBT (No Bus Turn Around) functionality allows zero wait be used to override the synchronous control of the output read-write-read bus utilization Fully pin-compatible with drivers and turn the RAM s output drivers off at any time. both pipelined and flow through NtRAM, NoBL and Write cycles are internally self-timed and initiated by the rising ZBT SRAMs edge of the clock input. This feature eliminates complex off- 2.5 V or 3.3 V +10%/10% core power supply chip write pulse generation required by asynchronous SRAMs 2.5 V or 3.3 V I/O supply and simplifies input signal timing. User-configurable Pipeline and Flow Through mode LBO pin for Linear or Interleave Burst mode The GS880Z18/32/36CT may be configured by the user to Pin compatible with 2M, 4M, and 18M devices operate in Pipeline or Flow Through mode. Operating as a Byte write operation (9-bit Bytes) pipelined synchronous device, meaning that in addition to the 3 chip enable signals for easy depth expansion rising edge triggered registers that capture input signals, the ZZ Pin for automatic power-down device incorporates a rising-edge-triggered output register. For JEDEC-standard 100-lead TQFP package read cycles, pipelined SRAM output data is temporarily stored RoHS-compliant 100-lead TQFP package available by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of Functional Description clock. The GS880Z18/32/36CT is a 9Mbit Synchronous Static The GS880Z18/32/36CT is implemented with GSI s high SRAM. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL or performance CMOS technology and is available in a JEDEC- other pipelined read/double late write or flow through read/ standard 100-pin TQFP package. single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power Parameter Synopsis -333 -300 -250 -200 -150 Unit t 2.5 2.5 2.5 3.0 3.8 ns KQ 3.0 3.3 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 240 225 195 170 140 mA Curr (x32/x36) 280 260 225 195 160 mA t 4.5 5.0 5.5 6.5 7.5 ns KQ tCycle 4.5 5.0 5.5 6.5 7.5 ns Flow Through 2-1-1-1 Curr (x18) 180 165 160 140 128 mA Curr (x32/x36) 205 190 180 160 145 mA Rev: 1.04 7/2012 1/24 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS880Z18/32/36CT-xxx GS880Z18CT 100-Pin TQFP Pinout (Package T) 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 512K x 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 FT 67 SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either V or V . These pins can also be left floating. DD SS Rev: 1.04 7/2012 2/24 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see